Simulation Results: hmac

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.10 %
  • code
  • 97.40 %
  • assert
  • 96.42 %
  • func
  • 43.48 %
  • line
  • 99.74 %
  • branch
  • 99.50 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.310s 241.405us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.880s 23.698us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.960s 16.975us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.180s 371.651us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.720s 163.011us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.610s 131.715us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.960s 16.975us 1 1 100.00
hmac_csr_aliasing 2.720s 163.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 42.170s 4686.022us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 28.390s 2100.377us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.980s 493.256us 1 1 100.00
hmac_test_sha384_vectors 284.880s 35947.147us 1 1 100.00
hmac_test_sha512_vectors 349.660s 11505.650us 1 1 100.00
hmac_test_hmac256_vectors 6.060s 1610.828us 1 1 100.00
hmac_test_hmac384_vectors 8.060s 539.364us 1 1 100.00
hmac_test_hmac512_vectors 10.890s 329.636us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.910s 1186.506us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 259.210s 8701.834us 1 1 100.00
error 1 1 100.00
hmac_error 7.950s 818.421us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 29.280s 1859.632us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.310s 241.405us 1 1 100.00
hmac_long_msg 42.170s 4686.022us 1 1 100.00
hmac_back_pressure 28.390s 2100.377us 1 1 100.00
hmac_datapath_stress 259.210s 8701.834us 1 1 100.00
hmac_burst_wr 6.910s 1186.506us 1 1 100.00
hmac_stress_all 158.330s 12866.401us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.310s 241.405us 1 1 100.00
hmac_long_msg 42.170s 4686.022us 1 1 100.00
hmac_back_pressure 28.390s 2100.377us 1 1 100.00
hmac_datapath_stress 259.210s 8701.834us 1 1 100.00
hmac_wipe_secret 29.280s 1859.632us 1 1 100.00
hmac_test_sha256_vectors 7.980s 493.256us 1 1 100.00
hmac_test_sha384_vectors 284.880s 35947.147us 1 1 100.00
hmac_test_sha512_vectors 349.660s 11505.650us 1 1 100.00
hmac_test_hmac256_vectors 6.060s 1610.828us 1 1 100.00
hmac_test_hmac384_vectors 8.060s 539.364us 1 1 100.00
hmac_test_hmac512_vectors 10.890s 329.636us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.310s 241.405us 1 1 100.00
hmac_long_msg 42.170s 4686.022us 1 1 100.00
hmac_back_pressure 28.390s 2100.377us 1 1 100.00
hmac_datapath_stress 259.210s 8701.834us 1 1 100.00
hmac_burst_wr 6.910s 1186.506us 1 1 100.00
hmac_error 7.950s 818.421us 1 1 100.00
hmac_wipe_secret 29.280s 1859.632us 1 1 100.00
hmac_test_sha256_vectors 7.980s 493.256us 1 1 100.00
hmac_test_sha384_vectors 284.880s 35947.147us 1 1 100.00
hmac_test_sha512_vectors 349.660s 11505.650us 1 1 100.00
hmac_test_hmac256_vectors 6.060s 1610.828us 1 1 100.00
hmac_test_hmac384_vectors 8.060s 539.364us 1 1 100.00
hmac_test_hmac512_vectors 10.890s 329.636us 1 1 100.00
hmac_stress_all 158.330s 12866.401us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 158.330s 12866.401us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 73.270us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.730s 14.097us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.370s 74.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.370s 74.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.880s 23.698us 1 1 100.00
hmac_csr_rw 0.960s 16.975us 1 1 100.00
hmac_csr_aliasing 2.720s 163.011us 1 1 100.00
hmac_same_csr_outstanding 2.160s 163.418us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.880s 23.698us 1 1 100.00
hmac_csr_rw 0.960s 16.975us 1 1 100.00
hmac_csr_aliasing 2.720s 163.011us 1 1 100.00
hmac_same_csr_outstanding 2.160s 163.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.170s 360.008us 1 1 100.00
hmac_tl_intg_err 2.660s 710.097us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.660s 710.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.310s 241.405us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.590s 126.044us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 74.470s 30949.120us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.170s 309.511us 1 1 100.00

Error Messages

   Test seed line log context