i2c Simulation Results

Simulation Results: i2c

15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.93 %

code
81.84 %

assert
95.98 %

func
82.98 %

line
96.57 %

branch
92.62 %

cond
86.88 %

toggle
89.66 %

FSM
43.45 %

Validation stages

V1		100.00%
V2		93.88%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	23.720s	5463.609us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	8.650s	1836.552us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.740s	69.146us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.660s	34.497us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.460s	747.123us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.400s	409.354us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.720s	25.558us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.660s	34.497us	1	1	100.00
	i2c_csr_aliasing	1.400s	409.354us	1	1	100.00

46/49 passed

93.88 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.130s	142.752us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	764.930s	25953.829us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	7.750s	2349.042us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.640s	54.983us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	37.180s	14024.551us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	24.940s	5635.964us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.940s	438.057us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.710s	683.545us	1	1	100.00
	i2c_host_fifo_reset_rx	5.370s	163.976us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	71.930s	2077.486us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	20.220s	3042.682us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.070s	357.900us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.020s	2183.642us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	398.460s	46903.450us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.230s	691.339us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	48.320s	11335.917us	1	1	100.00
	i2c_target_intr_smoke	3.260s	3764.324us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.770s	161.041us	1	1	100.00
	i2c_target_fifo_reset_tx	0.880s	494.738us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	354.630s	41471.988us	1	1	100.00
	i2c_target_stress_rd	48.320s	11335.917us	1	1	100.00
	i2c_target_intr_stress_wr	44.200s	12203.663us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.790s	3009.269us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.230s	259.524us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.960s	1925.426us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.630s	1164.532us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.890s	1820.969us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.900s	2052.327us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	7.750s	2349.042us	1	1	100.00
	i2c_host_perf_precise	0.880s	178.618us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	20.220s	3042.682us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.150s	180.362us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.000s	931.080us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.580s	464.258us	1	1	100.00
	i2c_target_nack_txstretch	1.160s	182.423us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.210s	281.666us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.360s	848.647us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.630s	22.972us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.630s	35.082us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.080s	156.339us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.080s	156.339us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.740s	69.146us	1	1	100.00
	i2c_csr_rw	0.660s	34.497us	1	1	100.00
	i2c_csr_aliasing	1.400s	409.354us	1	1	100.00
	i2c_same_csr_outstanding	0.950s	105.637us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.740s	69.146us	1	1	100.00
	i2c_csr_rw	0.660s	34.497us	1	1	100.00
	i2c_csr_aliasing	1.400s	409.354us	1	1	100.00
	i2c_same_csr_outstanding	0.950s	105.637us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_sec_cm	0.790s	68.762us	1	1	100.00
	i2c_tl_intg_err	1.190s	236.461us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.190s	236.461us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	2.910s	791.359us	1
target_error_intr				1
	i2c_target_unexp_stop	0.720s	28.968us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	11.360s	2221.588us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	43701278192398045236038552192480527285059943450583961836190941460747223171266	91	UVM_ERROR @ 142752200 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 142752200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	55966518184838667459634057349314644543506832736690129031566149182953732778307	81	UVM_ERROR @ 2183642313 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 2183642313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])
	i2c_target_unexp_stop	109401014759625954116027293303014012956365689326085708310037627437872348415227	75	UVM_ERROR @ 28967599 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1]) UVM_INFO @ 28967599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	16686212028199881738680105627468023143347720872958094036008155426877565693872	89	UVM_ERROR @ 791358928 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 791358928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	8792737689384564822874182879079803033702276686529234329683457583751990517987	90	UVM_ERROR @ 2221588029 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 2221588029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:
	i2c_target_nack_txstretch	112238970265237198213581201841731011763401145755424176134196533870363862702444	75	UVM_ERROR @ 182422834 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0 UVM_INFO @ 182422834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---