Simulation Results: lc_ctrl

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.18 %
  • code
  • 82.30 %
  • assert
  • 93.85 %
  • func
  • 82.38 %
  • line
  • 97.08 %
  • branch
  • 93.51 %
  • cond
  • 79.31 %
  • toggle
  • 73.52 %
  • FSM
  • 68.09 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.080s 216.487us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.920s 42.709us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 48.448us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.150s 74.221us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 65.372us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.370s 36.147us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 48.448us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 65.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3.990s 35.411us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 14.730s 337.408us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.910s 21.780us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.390s 97.302us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.800s 1267.873us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_prog_failure 2.390s 97.302us 1 1 100.00
lc_ctrl_errors 7.800s 1267.873us 1 1 100.00
lc_ctrl_security_escalation 5.690s 198.105us 1 1 100.00
lc_ctrl_jtag_state_failure 2.100s 339.824us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.790s 305.486us 1 1 100.00
lc_ctrl_jtag_errors 26.980s 2412.854us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 8.130s 445.536us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.050s 2698.530us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.790s 305.486us 1 1 100.00
lc_ctrl_jtag_errors 26.980s 2412.854us 1 1 100.00
lc_ctrl_jtag_access 1.110s 183.071us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.550s 4212.387us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.380s 458.761us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.930s 61.867us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.840s 678.596us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.910s 185.269us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.110s 132.035us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.490s 296.886us 1 1 100.00
lc_ctrl_jtag_alert_test 1.400s 45.914us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.300s 746.867us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.130s 23.986us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 1.720s 30.746us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.310s 28.968us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.360s 71.278us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.360s 71.278us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 42.709us 1 1 100.00
lc_ctrl_csr_rw 0.810s 48.448us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 65.372us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.080s 24.192us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 42.709us 1 1 100.00
lc_ctrl_csr_rw 0.810s 48.448us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 65.372us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.080s 24.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
lc_ctrl_tl_intg_err 1.880s 128.705us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.880s 128.705us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 14.730s 337.408us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 6.330s 987.201us 0 1 0.00
lc_ctrl_sec_cm 5.560s 259.497us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.690s 198.105us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3.990s 35.411us 0 1 0.00
lc_ctrl_jtag_state_post_trans 7.050s 2698.530us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.000s 4941.641us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.000s 4941.641us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.980s 419.450us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.290s 1205.665us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.290s 1205.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 17.080s 11494.898us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 13696360128813541645810828770493972717162975774705201718712842209422284701896 1185
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 987200978 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 987200978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 105051223122937058662213530313001168819743636801786855470327656292028890370929 580
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 35410589 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 35410589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 57162896679487221145463853452474483647548290951298798658657570554448956952871 331
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 339823687 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 339823687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 48075873636776275261811477808154337831049301995151740191205655678313237358272 570
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2698529618 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2698529618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 33225841574649893387825770034502889774580419979827774744444586203124100743675 329
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 30745894 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 30745894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20901660622973091046975958202552007546559607439467311122069028228188805194456 1712
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 11494898052 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 11494898052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---