Simulation Results: lc_ctrl

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.40 %
  • code
  • 84.22 %
  • assert
  • 94.13 %
  • func
  • 89.86 %
  • line
  • 96.97 %
  • branch
  • 93.32 %
  • cond
  • 78.87 %
  • toggle
  • 81.40 %
  • FSM
  • 70.53 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.130s 151.202us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.040s 26.943us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.770s 33.780us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.290s 71.854us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.640s 36.563us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.260s 62.795us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.770s 33.780us 1 1 100.00
lc_ctrl_csr_aliasing 1.640s 36.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.920s 663.373us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.290s 3275.864us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.800s 44.451us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.600s 76.959us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.580s 1495.745us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_prog_failure 2.600s 76.959us 1 1 100.00
lc_ctrl_errors 8.580s 1495.745us 1 1 100.00
lc_ctrl_security_escalation 4.180s 492.212us 1 1 100.00
lc_ctrl_jtag_state_failure 7.260s 3833.416us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.520s 161.467us 1 1 100.00
lc_ctrl_jtag_errors 15.880s 3496.226us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.030s 595.435us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.660s 970.276us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.520s 161.467us 1 1 100.00
lc_ctrl_jtag_errors 15.880s 3496.226us 1 1 100.00
lc_ctrl_jtag_access 4.280s 4553.961us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.650s 13091.564us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.200s 222.552us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.120s 234.304us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.680s 2299.089us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 12.100s 788.291us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.130s 80.865us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.730s 258.945us 1 1 100.00
lc_ctrl_jtag_alert_test 1.940s 125.762us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.170s 473.525us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.240s 17.591us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 30.720s 4959.378us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.740s 51.587us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.450s 27.576us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.450s 27.576us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.040s 26.943us 1 1 100.00
lc_ctrl_csr_rw 0.770s 33.780us 1 1 100.00
lc_ctrl_csr_aliasing 1.640s 36.563us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.610s 282.846us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.040s 26.943us 1 1 100.00
lc_ctrl_csr_rw 0.770s 33.780us 1 1 100.00
lc_ctrl_csr_aliasing 1.640s 36.563us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.610s 282.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
lc_ctrl_tl_intg_err 2.370s 86.886us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.370s 86.886us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.290s 3275.864us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.370s 15.477us 0 1 0.00
lc_ctrl_sec_cm 7.640s 1034.860us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.180s 492.212us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.920s 663.373us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.660s 970.276us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.310s 289.634us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.310s 289.634us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.600s 5716.656us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.370s 475.317us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.370s 475.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 11.550s 1997.822us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 156944737536865050861411850722267955544921150342598200273712266506468294816 215
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 15477277 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 15477277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 84978309963792613430861299111805466266557859269623560522541473566548501983594 571
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3833415853 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3833415853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 85070214837105252670098229934784010909138045723633112159334132375699700932008 218
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 4959377512 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4959377512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40043133657253152920855195016389133826940157709556495775357475214499536350270 1287
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1997822477 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1997822477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---