otp_ctrl Simulation Results

Simulation Results: otp_ctrl

15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
79.25 %

code
75.84 %

assert
94.04 %

func
67.88 %

line
88.29 %

branch
83.12 %

cond
89.66 %

toggle
74.38 %

FSM
43.75 %

Validation stages

V1		90.91%
V2		88.00%
V2S		94.64%
V3		50.00%

10/11 passed

90.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	3.430s	704.300us	1	1	100.00
smoke				1	1	100.00
	otp_ctrl_smoke	6.470s	1220.650us	1	1	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	1.930s	407.156us	1	1	100.00
csr_rw				1	1	100.00
	otp_ctrl_csr_rw	1.380s	93.466us	1	1	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	6.410s	426.472us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	2.240s	120.747us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	otp_ctrl_csr_mem_rw_with_rand_reset	1.540s	429.034us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	otp_ctrl_csr_rw	1.380s	93.466us	1	1	100.00
	otp_ctrl_csr_aliasing	2.240s	120.747us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	1.100s	43.426us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.350s	139.416us	1	1	100.00

22/25 passed

88.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				1	1	100.00
	otp_ctrl_partition_walk	13.240s	325.762us	1	1	100.00
init_fail				1	1	100.00
	otp_ctrl_init_fail	4.260s	145.705us	1	1	100.00
partition_check				1	2	50.00
	otp_ctrl_background_chks	6.530s	1292.820us	0	1	0.00
	otp_ctrl_check_fail	9.900s	1137.570us	1	1	100.00
regwen_during_otp_init				1	1	100.00
	otp_ctrl_regwen	2.390s	132.045us	1	1	100.00
partition_lock				1	1	100.00
	otp_ctrl_dai_lock	7.350s	502.785us	1	1	100.00
interface_key_check				1	1	100.00
	otp_ctrl_parallel_key_req	22.910s	2101.164us	1	1	100.00
lc_interactions				2	2	100.00
	otp_ctrl_parallel_lc_req	12.850s	1066.422us	1	1	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
otp_dai_errors				1	1	100.00
	otp_ctrl_dai_errs	11.120s	558.064us	1	1	100.00
otp_macro_errors				0	1	0.00
	otp_ctrl_macro_errs	4.820s	445.997us	0	1	0.00
test_access				1	1	100.00
	otp_ctrl_test_access	12.210s	4005.855us	1	1	100.00
stress_all				0	1	0.00
	otp_ctrl_stress_all	28.540s	5420.631us	0	1	0.00
intr_test				1	1	100.00
	otp_ctrl_intr_test	1.150s	78.791us	1	1	100.00
alert_test				1	1	100.00
	otp_ctrl_alert_test	2.760s	325.507us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	otp_ctrl_tl_errors	3.480s	396.462us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	otp_ctrl_tl_errors	3.480s	396.462us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	otp_ctrl_csr_hw_reset	1.930s	407.156us	1	1	100.00
	otp_ctrl_csr_rw	1.380s	93.466us	1	1	100.00
	otp_ctrl_csr_aliasing	2.240s	120.747us	1	1	100.00
	otp_ctrl_same_csr_outstanding	1.880s	100.240us	1	1	100.00
tl_d_partial_access				4	4	100.00
	otp_ctrl_csr_hw_reset	1.930s	407.156us	1	1	100.00
	otp_ctrl_csr_rw	1.380s	93.466us	1	1	100.00
	otp_ctrl_csr_aliasing	2.240s	120.747us	1	1	100.00
	otp_ctrl_same_csr_outstanding	1.880s	100.240us	1	1	100.00

V2S

53/56 passed

94.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
tl_intg_err				2	2	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
	otp_ctrl_tl_intg_err	8.210s	954.165us	1	1	100.00
prim_count_check				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
prim_fsm_check				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	otp_ctrl_tl_intg_err	8.210s	954.165us	1	1	100.00
sec_cm_secret_mem_scramble				1	1	100.00
	otp_ctrl_smoke	6.470s	1220.650us	1	1	100.00
sec_cm_part_mem_digest				1	1	100.00
	otp_ctrl_smoke	6.470s	1220.650us	1	1	100.00
sec_cm_dai_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_kdi_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_lci_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_part_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_scrmbl_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_timer_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_dai_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_kdi_seed_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_kdi_entropy_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_lci_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_part_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_scrmbl_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_timer_integ_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_timer_cnsty_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_timer_lfsr_redun				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_dai_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_lci_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
sec_cm_kdi_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
sec_cm_part_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
	otp_ctrl_macro_errs	4.820s	445.997us	0	1	0.00
sec_cm_scrmbl_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
sec_cm_timer_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_dai_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_lci_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
sec_cm_kdi_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
sec_cm_part_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
	otp_ctrl_macro_errs	4.820s	445.997us	0	1	0.00
sec_cm_scrmbl_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
sec_cm_timer_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	23.710s	3946.909us	1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_part_data_reg_integrity				1	1	100.00
	otp_ctrl_init_fail	4.260s	145.705us	1	1	100.00
sec_cm_part_data_reg_bkgn_chk				1	1	100.00
	otp_ctrl_check_fail	9.900s	1137.570us	1	1	100.00
sec_cm_part_mem_regren				1	1	100.00
	otp_ctrl_dai_lock	7.350s	502.785us	1	1	100.00
sec_cm_part_mem_sw_unreadable				1	1	100.00
	otp_ctrl_dai_lock	7.350s	502.785us	1	1	100.00
sec_cm_part_mem_sw_unwritable				1	1	100.00
	otp_ctrl_dai_lock	7.350s	502.785us	1	1	100.00
sec_cm_lc_part_mem_sw_noaccess				1	1	100.00
	otp_ctrl_dai_lock	7.350s	502.785us	1	1	100.00
sec_cm_access_ctrl_mubi				1	1	100.00
	otp_ctrl_dai_lock	7.350s	502.785us	1	1	100.00
sec_cm_token_valid_ctrl_mubi				1	1	100.00
	otp_ctrl_smoke	6.470s	1220.650us	1	1	100.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	otp_ctrl_dai_lock	7.350s	502.785us	1	1	100.00
sec_cm_test_bus_lc_gated				1	1	100.00
	otp_ctrl_smoke	6.470s	1220.650us	1	1	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	135.600s	35582.153us	1	1	100.00
sec_cm_direct_access_config_regwen				1	1	100.00
	otp_ctrl_regwen	2.390s	132.045us	1	1	100.00
sec_cm_check_trigger_config_regwen				1	1	100.00
	otp_ctrl_smoke	6.470s	1220.650us	1	1	100.00
sec_cm_check_config_regwen				1	1	100.00
	otp_ctrl_smoke	6.470s	1220.650us	1	1	100.00
sec_cm_macro_mem_integrity				0	1	0.00
	otp_ctrl_macro_errs	4.820s	445.997us	0	1	0.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				1	1	100.00
	otp_ctrl_low_freq_read	16.330s	5909.026us	1	1	100.00
stress_all_with_rand_reset				0	1	0.00
	otp_ctrl_stress_all_with_rand_reset	1.430s	53.825us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!
	otp_ctrl_background_chks	89645974132458356776397837919755876799502171919838022897181224809728000308933	4769	UVM_ERROR @ 1292819539 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger! UVM_INFO @ 1292819539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	81695589952919252214343197106578365232503062155378147261805495981684282648761	27034	UVM_ERROR @ 5420631390 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger! UVM_INFO @ 5420631390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_
	otp_ctrl_macro_errs	39696695276530767512657436703965870013024538881061386806478624060613224621443	5271	UVM_ERROR @ 445997057 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0 UVM_INFO @ 445997057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =
	otp_ctrl_stress_all_with_rand_reset	9194636566180698532256747001255678927947882332475803856955602786150603027906	89	UVM_ERROR @ 53824507 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1 UVM_INFO @ 53824507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)'
	otp_ctrl_csr_mem_rw_with_rand_reset	44136005575210134969836874795468942152515438023148925214826200181805270881956	90	Offending '(cio_test_en_o == 0)' UVM_ERROR @ 429033898 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A UVM_INFO @ 429033898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---