Simulation Results: pattgen

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 39.037us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 23.401us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 19.144us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 191.791us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 35.932us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 41.550us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 19.144us 1 1 100.00
pattgen_csr_aliasing 1.000s 35.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 0.000s 0.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 6.000s 786.873us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 24.316us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 552.000s 89453.234us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 13.673us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 99.769us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 221.381us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 221.381us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 23.401us 1 1 100.00
pattgen_csr_rw 1.000s 19.144us 1 1 100.00
pattgen_csr_aliasing 1.000s 35.932us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 54.136us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 23.401us 1 1 100.00
pattgen_csr_rw 1.000s 19.144us 1 1 100.00
pattgen_csr_aliasing 1.000s 35.932us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 54.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 36.842us 1 1 100.00
pattgen_tl_intg_err 2.000s 304.891us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 304.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 36.000s 18475.256us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 43.537us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes
pattgen_perf 111203932713139024655615735497956479363537208536195748496084816128886943291609 None
Job timed out after 60 minutes
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 8781312094450513005182769080156583831005972539038445391666508360440176628563 117
UVM_ERROR @ 3897930647 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3897947688 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3897947688 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 3898364358 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]