Simulation Results: rom_ctrl

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.91 %
  • code
  • 98.58 %
  • assert
  • 95.49 %
  • func
  • 96.66 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 94.95 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.130s 579.883us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.730s 210.122us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.750s 557.213us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.910s 2513.788us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 126.033us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.290s 359.062us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.750s 557.213us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 126.033us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.400s 166.347us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.060s 278.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.830s 173.149us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.280s 594.024us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.960s 922.331us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.620s 126.183us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.120s 538.227us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.120s 538.227us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.730s 210.122us 1 1 100.00
rom_ctrl_csr_rw 3.750s 557.213us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 126.033us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.960s 327.209us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.730s 210.122us 1 1 100.00
rom_ctrl_csr_rw 3.750s 557.213us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 126.033us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.960s 327.209us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.560s 3165.280us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 191.640s 1739.464us 0 1 0.00
rom_ctrl_tl_intg_err 23.160s 976.231us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 191.640s 1739.464us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 191.640s 1739.464us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 191.640s 1739.464us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 191.640s 1739.464us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.130s 579.883us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.130s 579.883us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.130s 579.883us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.160s 976.231us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
rom_ctrl_kmac_err_chk 5.960s 922.331us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.050s 4805.433us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.560s 3165.280us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 191.640s 1739.464us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 81.690s 3235.706us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 3196074564840497013069809478547886490349036044987943129454115679600851038886 183
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 29004132ps failed at 29004132ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 29004132ps failed at 29004132ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'