Simulation Results: rom_ctrl

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.39 %
  • code
  • 97.92 %
  • assert
  • 96.65 %
  • func
  • 97.61 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.190s 567.306us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.350s 923.840us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.070s 213.584us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.860s 1688.152us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 11.800s 4514.785us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.520s 222.521us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.070s 213.584us 1 1 100.00
rom_ctrl_csr_aliasing 11.800s 4514.785us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.270s 216.112us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.550s 290.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.160s 599.894us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 33.240s 1088.440us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.470s 1058.918us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.210s 383.690us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 12.800s 288.666us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 12.800s 288.666us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.350s 923.840us 1 1 100.00
rom_ctrl_csr_rw 6.070s 213.584us 1 1 100.00
rom_ctrl_csr_aliasing 11.800s 4514.785us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.440s 290.498us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.350s 923.840us 1 1 100.00
rom_ctrl_csr_rw 6.070s 213.584us 1 1 100.00
rom_ctrl_csr_aliasing 11.800s 4514.785us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.440s 290.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.650s 751.065us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 237.510s 391.556us 1 1 100.00
rom_ctrl_tl_intg_err 53.950s 579.463us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 237.510s 391.556us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 237.510s 391.556us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 237.510s 391.556us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 237.510s 391.556us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.190s 567.306us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.190s 567.306us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.190s 567.306us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 53.950s 579.463us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
rom_ctrl_kmac_err_chk 14.470s 1058.918us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.230s 8361.868us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.650s 751.065us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 237.510s 391.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 57.090s 6909.309us 1 1 100.00

Error Messages

   Test seed line log context