Simulation Results: rstmgr

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.16 %
  • code
  • 99.11 %
  • assert
  • 97.86 %
  • func
  • 97.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 97.92 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.640s 198.828us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.790s 96.158us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.990s 63.534us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.610s 821.879us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.900s 367.582us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.470s 173.039us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.990s 63.534us 1 1 100.00
rstmgr_csr_aliasing 1.900s 367.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.800s 167.820us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.850s 313.871us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.220s 306.618us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.570s 1482.495us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.570s 1482.495us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.570s 1482.495us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.570s 1482.495us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 22.150s 8472.774us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.060s 68.736us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.700s 265.198us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.700s 265.198us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.790s 96.158us 1 1 100.00
rstmgr_csr_rw 0.990s 63.534us 1 1 100.00
rstmgr_csr_aliasing 1.900s 367.582us 1 1 100.00
rstmgr_same_csr_outstanding 1.190s 123.860us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.790s 96.158us 1 1 100.00
rstmgr_csr_rw 0.990s 63.534us 1 1 100.00
rstmgr_csr_aliasing 1.900s 367.582us 1 1 100.00
rstmgr_same_csr_outstanding 1.190s 123.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 2.770s 920.251us 1 1 100.00
rstmgr_sec_cm 11.250s 8434.883us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.250s 8434.883us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.250s 8434.883us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.770s 920.251us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.870s 115.315us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.300s 1965.299us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.130s 301.609us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.250s 8434.883us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.990s 63.534us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.990s 63.534us 1 1 100.00

Error Messages

   Test seed line log context