Simulation Results: rv_timer

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.57 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.790s 275.270us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.640s 28.833us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.600s 12.207us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.230s 575.556us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.770s 33.465us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.840s 35.277us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.600s 12.207us 1 1 100.00
rv_timer_csr_aliasing 0.770s 33.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.700s 413.994us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.960s 5487.871us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 371.190s 1498498.671us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 371.190s 1498498.671us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.440s 6136.509us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.560s 15.321us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.580s 18.306us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.140s 51.715us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.140s 51.715us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 28.833us 1 1 100.00
rv_timer_csr_rw 0.600s 12.207us 1 1 100.00
rv_timer_csr_aliasing 0.770s 33.465us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 78.250us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 28.833us 1 1 100.00
rv_timer_csr_rw 0.600s 12.207us 1 1 100.00
rv_timer_csr_aliasing 0.770s 33.465us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 78.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_tl_intg_err 1.460s 464.528us 1 1 100.00
rv_timer_sec_cm 0.740s 227.210us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.460s 464.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.220s 214.000us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.770s 45.963us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 37.970s 9599.728us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 9624299023019816815925159290842908876493541444012869743915805343908684767143 72
UVM_FATAL @ 213999764 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd9907f04) == 0x1
UVM_INFO @ 213999764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 6846681320022233532196606177588931744316803869231150120652776093288501726571 72
UVM_FATAL @ 413993581 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x822ff304) == 0x1
UVM_INFO @ 413993581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 103722671774532686073775455466446966138797439339746664201696770953430336034891 75
UVM_ERROR @ 45962552 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45962552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---