Simulation Results: spi_device

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.14 %
  • code
  • 94.13 %
  • assert
  • 94.14 %
  • func
  • 73.16 %
  • line
  • 99.11 %
  • branch
  • 98.33 %
  • cond
  • 96.13 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 20.000s 7041.120us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.210s 73.324us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.250s 101.916us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.720s 189.798us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.060s 818.395us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.620s 184.632us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.250s 101.916us 1 1 100.00
spi_device_csr_aliasing 10.060s 818.395us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.780s 13.175us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.710s 105.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.720s 19.037us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.860s 15.944us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.640s 20.221us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.150s 176.716us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.150s 176.716us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.980s 1998.615us 1 1 100.00
spi_device_tpm_sts_read 0.740s 57.098us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 5.730s 1378.158us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.610s 6686.869us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 18.770s 23519.030us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 18.770s 23519.030us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.030s 2567.110us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.030s 2567.110us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.030s 2567.110us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.030s 2567.110us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.030s 2567.110us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 9.860s 18077.278us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 9.860s 3796.598us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 9.860s 3796.598us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 9.860s 3796.598us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.620s 678.283us 1 1 100.00
spi_device_read_buffer_direct 8.710s 1571.520us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 9.860s 3796.598us 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 28.120s 5735.527us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.720s 87.850us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.720s 87.850us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 20.000s 7041.120us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 215.370s 40889.762us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 313.900s 190289.653us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.650s 40.425us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.690s 50.171us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.160s 368.791us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.160s 368.791us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.210s 73.324us 1 1 100.00
spi_device_csr_rw 2.250s 101.916us 1 1 100.00
spi_device_csr_aliasing 10.060s 818.395us 1 1 100.00
spi_device_same_csr_outstanding 1.680s 90.934us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.210s 73.324us 1 1 100.00
spi_device_csr_rw 2.250s 101.916us 1 1 100.00
spi_device_csr_aliasing 10.060s 818.395us 1 1 100.00
spi_device_same_csr_outstanding 1.680s 90.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.900s 67.802us 1 1 100.00
spi_device_tl_intg_err 10.370s 209.484us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.370s 209.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 22.780s 1621.718us 1 1 100.00

Error Messages

   Test seed line log context