Simulation Results: spi_host

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.25 %
  • code
  • 94.88 %
  • assert
  • 93.54 %
  • func
  • 88.33 %
  • block
  • 96.64 %
  • line
  • 98.47 %
  • branch
  • 93.05 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 12.000s 3262.843us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 18.545us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 25.860us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 170.475us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 84.484us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 88.242us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 25.860us 1 1 100.00
spi_host_csr_aliasing 2.000s 84.484us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 25.765us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 26.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 119.496us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 47.323us 1 1 100.00
spi_host_error_cmd 2.000s 23.061us 1 1 100.00
spi_host_event 19.000s 2497.481us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 97.308us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 97.308us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 97.308us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 183.318us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 27.122us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 97.308us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 97.308us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 12.000s 3262.843us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 12.000s 3262.843us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 412.597us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 205.674us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 14.000s 1709.671us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 45.075us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 47.323us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 54.413us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 38.709us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 94.632us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 94.632us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.545us 1 1 100.00
spi_host_csr_rw 1.000s 25.860us 1 1 100.00
spi_host_csr_aliasing 2.000s 84.484us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 36.339us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.545us 1 1 100.00
spi_host_csr_rw 1.000s 25.860us 1 1 100.00
spi_host_csr_aliasing 2.000s 84.484us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 36.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 165.142us 1 1 100.00
spi_host_tl_intg_err 1.000s 875.334us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 875.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
spi_host_upper_range_clkdiv 139.000s 200000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_upper_range_clkdiv 18387980190730731566813982777799302102371050611622831392281078536312267857792 139
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---