Simulation Results: sram_ctrl

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.79 %
  • code
  • 89.11 %
  • assert
  • 95.55 %
  • func
  • 90.72 %
  • line
  • 97.41 %
  • branch
  • 94.55 %
  • cond
  • 91.55 %
  • toggle
  • 90.62 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 16.970s 1399.583us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.800s 23.065us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.790s 13.663us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.190s 64.204us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 12.256us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.310s 369.064us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.790s 13.663us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 12.256us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 239.150s 14130.273us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 111.000s 5195.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 370.560s 11311.244us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 218.240s 4659.835us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1665.950s 31950.730us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 207.460s 14140.871us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 63.260s 16689.396us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 420.670s 4022.662us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 14.670s 5093.670us 1 1 100.00
sram_ctrl_partial_access_b2b 186.210s 9562.011us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 28.720s 3219.105us 1 1 100.00
sram_ctrl_throughput_w_partial_write 33.670s 784.624us 1 1 100.00
sram_ctrl_throughput_w_readback 10.720s 2864.103us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 58.440s 1589.571us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.740s 343.920us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1724.110s 69173.107us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.960s 196.123us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.610s 59.143us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.610s 59.143us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 23.065us 1 1 100.00
sram_ctrl_csr_rw 0.790s 13.663us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 12.256us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.950s 47.748us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 23.065us 1 1 100.00
sram_ctrl_csr_rw 0.790s 13.663us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 12.256us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.950s 47.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.230s 7265.729us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.930s 428.087us 1 1 100.00
sram_ctrl_sec_cm 0.870s 1.937us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.870s 1.937us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.930s 428.087us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 58.440s 1589.571us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 58.440s 1589.571us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.790s 13.663us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 420.670s 4022.662us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 420.670s 4022.662us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 420.670s 4022.662us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 63.260s 16689.396us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.910s 702.480us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.230s 7265.729us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.920s 1576.689us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 16.970s 1399.583us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 16.970s 1399.583us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 420.670s 4022.662us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.870s 1.937us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 63.260s 16689.396us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.870s 1.937us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.870s 1.937us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 16.970s 1399.583us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.870s 1.937us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.670s 613.522us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 109052548446831303495457023607751029440185833652572381744008228560512292589435 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 1937191 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1937191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---