Simulation Results: sysrst_ctrl

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.47 %
  • code
  • 89.88 %
  • assert
  • 88.70 %
  • func
  • 65.82 %
  • line
  • 95.46 %
  • branch
  • 96.18 %
  • cond
  • 93.03 %
  • toggle
  • 100.00 %
  • FSM
  • 64.74 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 5.340s 2114.940us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.100s 2467.623us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.690s 2432.625us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.950s 2500.837us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 6.750s 6035.246us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.850s 2031.883us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 53.490s 57293.488us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.080s 2798.816us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.960s 2068.420us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.850s 2031.883us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.080s 2798.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 25.640s 160843.850us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 85.690s 186105.576us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.430s 3435.672us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.820s 2888.894us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.580s 2509.853us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.790s 2236.188us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.020s 3531.786us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.710s 2614.783us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.540s 8776.756us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 30.500s 32502.714us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 5.770s 10180.088us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.270s 2015.046us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.700s 2022.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.560s 2021.469us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.560s 2021.469us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.750s 6035.246us 1 1 100.00
sysrst_ctrl_csr_rw 4.850s 2031.883us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.080s 2798.816us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 20.190s 10107.357us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.750s 6035.246us 1 1 100.00
sysrst_ctrl_csr_rw 4.850s 2031.883us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.080s 2798.816us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 20.190s 10107.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 19.560s 42561.833us 1 1 100.00
sysrst_ctrl_sec_cm 42.230s 22008.727us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 19.560s 42561.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 7.590s 3186.934us 1 1 100.00

Error Messages

   Test seed line log context