uart Simulation Results

Simulation Results: uart

15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.25 %

code
96.02 %

assert
97.12 %

func
62.60 %

line
99.06 %

branch
96.74 %

cond
96.73 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		97.06%
V2S		100.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	1.040s	754.321us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.570s	12.722us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.640s	33.483us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.100s	34.096us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.660s	61.969us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.670s	22.022us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.640s	33.483us	1	1	100.00
	uart_csr_aliasing	0.660s	61.969us	1	1	100.00

33/34 passed

97.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	1.250s	695.010us	1	1	100.00
parity				2	2	100.00
	uart_smoke	1.040s	754.321us	1	1	100.00
	uart_tx_rx	1.250s	695.010us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	4.610s	13695.437us	1	1	100.00
	uart_rx_parity_err	211.290s	217618.094us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	1.250s	695.010us	1	1	100.00
	uart_intr	4.610s	13695.437us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	70.230s	58500.821us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	17.810s	16224.961us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	15.450s	31421.292us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	4.610s	13695.437us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	4.610s	13695.437us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	4.610s	13695.437us	1	1	100.00
perf				1	1	100.00
	uart_perf	415.820s	10767.336us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	0.960s	1456.928us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	0.960s	1456.928us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	1.310s	2315.600us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	24.540s	42144.376us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	1.600s	1808.765us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	20.070s	6092.235us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	192.750s	192003.016us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	546.740s	208648.004us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.610s	48.532us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.560s	12.560us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.430s	45.511us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.430s	45.511us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.570s	12.722us	1	1	100.00
	uart_csr_rw	0.640s	33.483us	1	1	100.00
	uart_csr_aliasing	0.660s	61.969us	1	1	100.00
	uart_same_csr_outstanding	0.620s	22.789us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.570s	12.722us	1	1	100.00
	uart_csr_rw	0.640s	33.483us	1	1	100.00
	uart_csr_aliasing	0.660s	61.969us	1	1	100.00
	uart_same_csr_outstanding	0.620s	22.789us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.820s	284.775us	1	1	100.00
	uart_tl_intg_err	0.860s	185.313us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	0.860s	185.313us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	13.080s	5213.494us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *
	uart_noise_filter	22341081537247772908690585181492335839836299838352698372907008433747637808826	72	UVM_ERROR @ 1161800169 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 1529560169 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 1529560169 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1538640169 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 1538640169 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0