Simulation Results: adc_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.40 %
  • code
  • 95.93 %
  • assert
  • 95.95 %
  • func
  • 43.32 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 95.49 %
  • toggle
  • 100.00 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.850s 5966.088us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.290s 1422.676us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.280s 358.211us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 43.620s 50095.588us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.730s 1041.513us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.220s 685.152us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.280s 358.211us 1 1 100.00
adc_ctrl_csr_aliasing 3.730s 1041.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 203.120s 498508.952us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 261.080s 338211.455us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 276.920s 160810.270us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 150.580s 327706.473us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 387.140s 354166.773us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 80.490s 202003.729us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 267.090s 168513.344us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 71.890s 164772.344us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.240s 5461.512us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 16.860s 35242.025us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 14.130s 82537.975us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 817.240s 498309.714us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.390s 407.513us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.160s 325.964us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.000s 537.104us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.000s 537.104us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.290s 1422.676us 1 1 100.00
adc_ctrl_csr_rw 1.280s 358.211us 1 1 100.00
adc_ctrl_csr_aliasing 3.730s 1041.513us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.930s 5271.825us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.290s 1422.676us 1 1 100.00
adc_ctrl_csr_rw 1.280s 358.211us 1 1 100.00
adc_ctrl_csr_aliasing 3.730s 1041.513us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.930s 5271.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 12.750s 8452.146us 1 1 100.00
adc_ctrl_tl_intg_err 8.100s 4202.485us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 8.100s 4202.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 7.830s 9794.492us 1 1 100.00

Error Messages

   Test seed line log context