Simulation Results: alert_handler

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.66 %
  • code
  • 90.40 %
  • assert
  • 93.95 %
  • func
  • 75.62 %
  • line
  • 99.60 %
  • branch
  • 99.71 %
  • cond
  • 93.28 %
  • toggle
  • 90.04 %
  • FSM
  • 69.35 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 20.570s 561.090us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.990s 146.488us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.510s 109.846us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 232.330s 11442.119us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 157.540s 8398.613us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.590s 41.677us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.510s 109.846us 1 1 100.00
alert_handler_csr_aliasing 157.540s 8398.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 160.660s 10492.669us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 6.630s 311.518us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 582.960s 11119.369us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 5.870s 268.494us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 20.570s 561.090us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 22.400s 395.798us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 33.280s 3113.175us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 14.330s 934.999us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1380.620s 136908.368us 1 1 100.00
alert_handler_lpg_stub_clk 607.060s 60272.344us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 37.180s 2130.287us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 9.930s 1319.688us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.660s 62.836us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.110s 7.353us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.750s 218.339us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.750s 218.339us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.990s 146.488us 1 1 100.00
alert_handler_csr_rw 4.510s 109.846us 1 1 100.00
alert_handler_csr_aliasing 157.540s 8398.613us 1 1 100.00
alert_handler_same_csr_outstanding 8.190s 348.648us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.990s 146.488us 1 1 100.00
alert_handler_csr_rw 4.510s 109.846us 1 1 100.00
alert_handler_csr_aliasing 157.540s 8398.613us 1 1 100.00
alert_handler_same_csr_outstanding 8.190s 348.648us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 61.070s 1632.712us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 61.070s 1632.712us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 61.070s 1632.712us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 61.070s 1632.712us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 417.740s 4894.541us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_tl_intg_err 47.800s 1278.396us 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 47.800s 1278.396us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 61.070s 1632.712us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 20.570s 561.090us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 20.570s 561.090us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 20.570s 561.090us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 20.570s 561.090us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.870s 268.494us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1380.620s 136908.368us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.870s 268.494us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 582.960s 11119.369us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 582.960s 11119.369us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.650s 1010.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 55.400s 5758.770us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 75337182253996102119812600212512059298480651825150004388273426905155648146043 78
UVM_ERROR @ 934998959 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 934998959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 79357494678979672702807654241474879900280221618132354741412231607258118941581 121
UVM_ERROR @ 5758770489 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5758770489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---