Simulation Results: chip

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.08 %
  • code
  • 85.08 %
  • assert
  • 96.28 %
  • func
  • 43.88 %
  • line
  • 94.29 %
  • branch
  • 93.64 %
  • cond
  • 88.86 %
  • toggle
  • 91.45 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
87.01%
V2S
50.00%
V3
63.33%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 113.050s 2991.033us 1 1 100.00
chip_sw_example_rom 55.180s 2316.266us 1 1 100.00
chip_sw_example_manufacturer 139.580s 3110.694us 1 1 100.00
chip_sw_example_concurrency 166.540s 2674.260us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 125.060s 5486.337us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 193.040s 4375.341us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 462.860s 6081.335us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4353.330s 38801.225us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 55.180s 2190.673us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4353.330s 38801.225us 1 1 100.00
chip_csr_rw 193.040s 4375.341us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.800s 47.153us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 278.110s 4511.018us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 278.110s 4511.018us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 278.110s 4511.018us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 341.720s 4556.244us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 341.720s 4556.244us 1 1 100.00
chip_sw_uart_tx_rx_idx1 331.380s 4040.040us 1 1 100.00
chip_sw_uart_tx_rx_idx2 335.650s 3967.510us 1 1 100.00
chip_sw_uart_tx_rx_idx3 342.250s 4012.630us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 855.640s 7537.413us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1053.930s 8751.327us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 220.990s 4179.644us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 120.040s 4290.954us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 120.040s 4290.954us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 148.340s 2938.958us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 286.080s 5776.389us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 98.710s 2971.894us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 158.790s 4113.051us 1 1 100.00
chip_tap_straps_testunlock0 384.140s 6453.508us 1 1 100.00
chip_tap_straps_rma 139.140s 2947.959us 1 1 100.00
chip_tap_straps_prod 761.530s 12549.612us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 115.560s 2700.359us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 834.310s 9572.205us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 334.180s 5031.563us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 334.180s 5031.563us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 504.290s 6885.512us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1560.070s 16612.629us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 341.760s 4269.445us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 614.590s 6274.407us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3428.750s 19424.990us 1 1 100.00
chip_sw_aes_enc_jitter_en 148.760s 2933.282us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 726.320s 6965.381us 1 1 100.00
chip_sw_hmac_enc_jitter_en 175.240s 3601.621us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1280.760s 12167.932us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 152.170s 3047.991us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 336.300s 4423.913us 1 1 100.00
chip_sw_clkmgr_jitter 140.730s 2549.782us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 138.730s 2419.724us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 220.420s 4583.765us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 223.270s 4677.110us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 129.270s 2969.051us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 223.270s 4677.110us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 103.540s 2741.518us 1 1 100.00
chip_sw_aes_smoketest 138.840s 3082.415us 1 1 100.00
chip_sw_aon_timer_smoketest 169.640s 3295.460us 1 1 100.00
chip_sw_clkmgr_smoketest 98.110s 2403.904us 1 1 100.00
chip_sw_csrng_smoketest 112.360s 2285.545us 1 1 100.00
chip_sw_entropy_src_smoketest 639.140s 6013.750us 1 1 100.00
chip_sw_gpio_smoketest 170.450s 2946.232us 1 1 100.00
chip_sw_hmac_smoketest 155.460s 3057.765us 1 1 100.00
chip_sw_kmac_smoketest 175.380s 2733.894us 1 1 100.00
chip_sw_otbn_smoketest 631.990s 5971.182us 1 1 100.00
chip_sw_pwrmgr_smoketest 208.300s 5810.931us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 169.350s 5176.617us 1 1 100.00
chip_sw_rv_plic_smoketest 126.070s 3566.752us 1 1 100.00
chip_sw_rv_timer_smoketest 159.150s 2671.439us 1 1 100.00
chip_sw_rstmgr_smoketest 125.300s 2234.085us 1 1 100.00
chip_sw_sram_ctrl_smoketest 150.150s 3011.266us 1 1 100.00
chip_sw_uart_smoketest 175.820s 3325.299us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 151.140s 2725.649us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_functest 389.310s 5423.345us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7459.080s 62814.923us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2426.780s 14871.184us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 144.870s 4581.299us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 171.460s 3090.410us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 181.860s 2879.660us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6963.550s 54243.083us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7115.510s 55655.568us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 60.650s 2839.631us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 60.650s 2839.631us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4353.330s 38801.225us 1 1 100.00
chip_same_csr_outstanding 1135.430s 15527.937us 1 1 100.00
chip_csr_hw_reset 125.060s 5486.337us 1 1 100.00
chip_csr_rw 193.040s 4375.341us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4353.330s 38801.225us 1 1 100.00
chip_same_csr_outstanding 1135.430s 15527.937us 1 1 100.00
chip_csr_hw_reset 125.060s 5486.337us 1 1 100.00
chip_csr_rw 193.040s 4375.341us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 15.550s 274.138us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.700s 46.437us 1 1 100.00
xbar_smoke_large_delays 62.640s 10597.773us 1 1 100.00
xbar_smoke_slow_rsp 48.630s 5381.213us 1 1 100.00
xbar_random_zero_delays 27.060s 487.686us 1 1 100.00
xbar_random_large_delays 347.680s 59713.769us 1 1 100.00
xbar_random_slow_rsp 141.670s 17563.345us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 13.190s 154.999us 1 1 100.00
xbar_error_and_unmapped_addr 28.730s 1125.246us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 9.750s 131.424us 1 1 100.00
xbar_error_and_unmapped_addr 28.730s 1125.246us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 50.250s 1927.686us 1 1 100.00
xbar_access_same_device_slow_rsp 586.050s 67870.312us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 22.980s 1228.305us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 44.120s 750.089us 1 1 100.00
xbar_stress_all_with_error 82.510s 4334.244us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 144.080s 572.748us 1 1 100.00
xbar_stress_all_with_reset_error 175.880s 4457.768us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2426.780s 14871.184us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2262.020s 30014.170us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2377.750s 15386.713us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2023.420s 11864.806us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2605.930s 16303.384us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2523.340s 15508.567us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2480.330s 15735.647us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2499.210s 15403.856us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 17.300s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 16.440s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 20.000s 10.300us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 17.310s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 21.870s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 17.420s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 25.150s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 22.900s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 21.980s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.510s 10.120us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 17.970s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.740s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 21.890s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 28.110s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.550s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 17.210s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.270s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.870s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.520s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.290s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.470s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 18.290s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 19.580s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.370s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.340s 10.120us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1847.230s 11083.506us 1 1 100.00
rom_e2e_asm_init_dev 2534.470s 15312.980us 1 1 100.00
rom_e2e_asm_init_prod 2388.370s 16162.711us 1 1 100.00
rom_e2e_asm_init_prod_end 2424.970s 15527.129us 1 1 100.00
rom_e2e_asm_init_rma 2285.080s 15107.066us 1 1 100.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 2342.270s 16547.463us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 2299.310s 17710.578us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4113.450s 29594.302us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2379.090s 18905.953us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2949.380s 34789.849us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2949.380s 34789.849us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 172.930s 2946.922us 1 1 100.00
chip_sw_aes_enc_jitter_en 148.760s 2933.282us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 117.280s 2648.242us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 163.740s 2678.879us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1552.840s 11494.099us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 152.530s 2806.255us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 295.150s 5091.536us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 327.360s 5563.269us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 522.690s 5360.051us 1 1 100.00
chip_plic_all_irqs_10 265.300s 3589.386us 1 1 100.00
chip_plic_all_irqs_20 376.410s 5011.985us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 150.480s 2839.938us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 879.380s 11205.343us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 221.030s 3832.947us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 111.620s 2610.267us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 820.650s 7545.871us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 846.470s 6956.157us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 777.100s 7628.880us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8566.510s 255902.884us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 216.920s 3481.515us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 208.300s 5810.931us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 216.920s 3481.515us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 565.010s 7809.267us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 565.010s 7809.267us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 209.620s 5927.685us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 244.790s 4545.611us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 573.040s 5457.496us 1 1 100.00
chip_sw_aes_idle 163.740s 2678.879us 1 1 100.00
chip_sw_hmac_enc_idle 173.880s 3384.797us 1 1 100.00
chip_sw_kmac_idle 139.480s 2616.462us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 156.300s 3736.724us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 208.730s 3734.669us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 176.610s 4412.259us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 211.430s 4707.014us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 903.180s 10607.989us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 345.220s 3686.202us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 354.910s 4146.798us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 352.550s 4230.447us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 338.190s 4248.084us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 347.590s 3677.909us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 348.480s 4681.628us 1 1 100.00
chip_sw_ast_clk_outputs 504.290s 6885.512us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 574.150s 12371.179us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 352.550s 4230.447us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 338.190s 4248.084us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 341.760s 4269.445us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 614.590s 6274.407us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3428.750s 19424.990us 1 1 100.00
chip_sw_aes_enc_jitter_en 148.760s 2933.282us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 726.320s 6965.381us 1 1 100.00
chip_sw_hmac_enc_jitter_en 175.240s 3601.621us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1280.760s 12167.932us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 152.170s 3047.991us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 336.300s 4423.913us 1 1 100.00
chip_sw_clkmgr_jitter 140.730s 2549.782us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 145.480s 2800.761us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 363.710s 4044.984us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 659.500s 7129.835us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 2949.180s 24284.385us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 130.580s 3166.360us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 144.640s 3168.800us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 464.040s 7302.535us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 163.330s 2879.079us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 321.000s 5451.670us 1 1 100.00
chip_sw_flash_init_reduced_freq 1239.470s 20079.136us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2422.350s 24052.901us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 504.290s 6885.512us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 338.010s 4263.751us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 282.180s 4220.298us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 327.360s 5563.269us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 820.650s 7545.871us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 723.930s 6174.435us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 162.760s 3027.047us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 428.510s 5334.898us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 174.450s 3120.152us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4261.250s 26420.155us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 153.480s 3088.380us 1 1 100.00
chip_sw_edn_entropy_reqs 549.460s 5834.044us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 153.480s 3088.380us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 723.930s 6174.435us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 123.840s 3087.402us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1396.390s 19974.572us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 588.730s 6011.781us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 614.590s 6274.407us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 332.410s 4391.533us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 341.760s 4269.445us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3598.800s 43823.351us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1396.390s 19974.572us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 175.050s 3041.907us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 980.170s 8758.312us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 187.570s 4213.995us 1 1 100.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3598.800s 43823.351us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 187.570s 4213.995us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 187.570s 4213.995us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 187.570s 4213.995us 1 1 100.00
chip_sw_flash_lc_seed_hw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 187.570s 4213.995us 1 1 100.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 327.360s 5563.269us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 175.760s 9500.219us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 519.040s 4812.500us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 319.440s 4581.822us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 319.440s 4581.822us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 172.270s 3134.753us 1 1 100.00
chip_sw_hmac_enc_jitter_en 175.240s 3601.621us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 173.880s 3384.797us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 677.990s 5961.379us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 691.980s 5703.822us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 365.750s 4875.773us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 386.020s 5396.833us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 327.340s 4340.278us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 212.320s 3565.193us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 980.170s 8758.312us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1280.760s 12167.932us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 887.890s 7597.237us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1552.840s 11494.099us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2096.370s 11789.655us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 168.130s 2962.568us 1 1 100.00
chip_sw_kmac_mode_kmac 161.910s 2546.804us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 152.170s 3047.991us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 980.170s 8758.312us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 265.740s 5597.228us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 96.220s 2106.262us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 557.270s 5717.584us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 139.480s 2616.462us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 295.150s 5091.536us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 158.790s 4113.051us 1 1 100.00
chip_tap_straps_rma 139.140s 2947.959us 1 1 100.00
chip_tap_straps_prod 761.530s 12549.612us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 122.600s 3287.813us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 265.740s 5597.228us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 265.740s 5597.228us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 265.740s 5597.228us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1344.240s 11283.550us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 175.760s 9500.219us 1 1 100.00
chip_rv_dm_lc_disabled 183.200s 7457.023us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 187.570s 4213.995us 1 1 100.00
chip_sw_flash_rma_unlocked 3598.800s 43823.351us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 168.100s 2591.155us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 340.790s 5038.378us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 368.740s 5482.574us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 361.820s 6183.569us 0 1 0.00
chip_sw_lc_ctrl_transition 265.740s 5597.228us 1 1 100.00
chip_sw_keymgr_key_derivation 980.170s 8758.312us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 309.400s 8697.410us 1 1 100.00
chip_sw_sram_ctrl_execution_main 482.310s 7963.158us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 574.150s 12371.179us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 345.220s 3686.202us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 354.910s 4146.798us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 352.550s 4230.447us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 338.190s 4248.084us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 347.590s 3677.909us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 348.480s 4681.628us 1 1 100.00
chip_tap_straps_dev 158.790s 4113.051us 1 1 100.00
chip_tap_straps_rma 139.140s 2947.959us 1 1 100.00
chip_tap_straps_prod 761.530s 12549.612us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 176.150s 3708.445us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 113.300s 3939.916us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 97.770s 2848.853us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 93.390s 3442.415us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 183.200s 7457.023us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1780.420s 34886.870us 1 1 100.00
chip_sw_lc_walkthrough 5 5 100.00
chip_sw_lc_walkthrough_dev 3802.440s 49725.249us 1 1 100.00
chip_sw_lc_walkthrough_prod 3710.730s 50719.443us 1 1 100.00
chip_sw_lc_walkthrough_prodend 522.640s 9611.917us 1 1 100.00
chip_sw_lc_walkthrough_rma 3557.950s 48960.886us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1780.420s 34886.870us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 77.840s 2867.080us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 53.560s 1843.389us 1 1 100.00
rom_volatile_raw_unlock 64.440s 2458.768us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3344.910s 17192.242us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3428.750s 19424.990us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 573.040s 5457.496us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 573.040s 5457.496us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 573.040s 5457.496us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 252.290s 3547.144us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 265.740s 5597.228us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1396.390s 19974.572us 1 1 100.00
chip_sw_otbn_mem_scramble 252.290s 3547.144us 1 1 100.00
chip_sw_keymgr_key_derivation 980.170s 8758.312us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 235.270s 3967.920us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.780s 2768.993us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1396.390s 19974.572us 1 1 100.00
chip_sw_otbn_mem_scramble 252.290s 3547.144us 1 1 100.00
chip_sw_keymgr_key_derivation 980.170s 8758.312us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 235.270s 3967.920us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.780s 2768.993us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 265.740s 5597.228us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 331.180s 4567.186us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 122.600s 3287.813us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 175.760s 9500.219us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 168.100s 2591.155us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 340.790s 5038.378us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 368.740s 5482.574us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 361.820s 6183.569us 0 1 0.00
chip_sw_lc_ctrl_transition 265.740s 5597.228us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 175.760s 9500.219us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 827.640s 7038.840us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 298.930s 8754.796us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1166.340s 28887.268us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 223.980s 7359.318us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 224.160s 7016.908us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 292.860s 6424.181us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1303.940s 27221.580us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 733.040s 13881.993us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 565.010s 7809.267us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 754.260s 9696.768us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 251.590s 5256.021us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 298.930s 8754.796us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 157.100s 3570.738us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 903.400s 16106.067us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 215.480s 6203.665us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 359.040s 6392.112us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 453.200s 11707.909us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 524.970s 7752.480us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 719.520s 11118.601us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1388.170s 26074.118us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 145.830s 2967.918us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 327.360s 5563.269us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 309.400s 8697.410us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 309.400s 8697.410us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 719.520s 11118.601us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 453.200s 11707.909us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 251.590s 5256.021us 1 1 100.00
chip_sw_pwrmgr_smoketest 208.300s 5810.931us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 267.410s 4232.006us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 191.780s 3458.447us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 263.790s 4779.051us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 879.380s 11205.343us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 156.210s 3114.725us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 327.360s 5563.269us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 846.470s 6956.157us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 443.380s 5032.991us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 467.040s 4940.617us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 117.810s 2475.889us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.780s 2768.993us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 191.780s 3458.447us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 191.780s 3458.447us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 693.720s 10426.431us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 958.850s 14103.950us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 267.410s 4232.006us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 153.940s 2891.012us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 201.410s 5667.531us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 139.140s 2947.959us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 183.200s 7457.023us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 522.690s 5360.051us 1 1 100.00
chip_plic_all_irqs_10 265.300s 3589.386us 1 1 100.00
chip_plic_all_irqs_20 376.410s 5011.985us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 162.490s 2739.530us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 163.400s 2721.876us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2426.780s 14871.184us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 516.510s 7560.191us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 183.190s 3040.152us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 200.290s 3396.281us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 169.420s 2730.739us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 235.270s 3967.920us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 336.300s 4423.913us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 389.640s 8684.101us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 324.800s 8617.122us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 482.310s 7963.158us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 327.360s 5563.269us 1 1 100.00
chip_sw_data_integrity_escalation 334.180s 5031.563us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 524.970s 7752.480us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1259.560s 25271.457us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 144.340s 2776.248us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 189.500s 3569.517us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 316.150s 5099.664us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1259.560s 25271.457us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1259.560s 25271.457us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2248.690s 20229.923us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2248.690s 20229.923us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 273.760s 6505.620us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2949.380s 34789.849us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 106.860s 3064.234us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 142.760s 3404.557us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 298.120s 3734.462us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 305.420s 3284.956us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 950.290s 8559.543us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4957.940s 32161.337us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1787.110s 11764.920us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 170.960s 3351.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 150.740s 3035.901us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 89.860s 2600.682us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9043.070s 71770.718us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1055.810s 6353.269us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 159.310s 3643.099us 0 1 0.00
rom_e2e_jtag_debug_dev 175.410s 3895.846us 0 1 0.00
rom_e2e_jtag_debug_rma 153.110s 4010.648us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 194.770s 4978.539us 0 1 0.00
rom_e2e_jtag_inject_dev 67.790s 2348.285us 0 1 0.00
rom_e2e_jtag_inject_rma 69.100s 2067.387us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 11.144s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 1 1 100.00
chip_sw_clkmgr_jitter_frequency 431.920s 4995.646us 1 1 100.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 281.270s 3042.926us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 768.750s 6091.894us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1269.030s 10090.294us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 222.250s 2780.844us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 569.580s 4839.095us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 55.630s 2379.270us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 189.300s 2755.775us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 287.430s 5696.796us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 321.600s 5200.638us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 719.520s 11118.601us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 159.310s 3643.099us 0 1 0.00
rom_e2e_jtag_debug_dev 175.410s 3895.846us 0 1 0.00
rom_e2e_jtag_debug_rma 153.110s 4010.648us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 240.210s 5341.037us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 327.360s 5563.269us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5220.750s 38366.025us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5220.750s 38366.025us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 122.960s 3419.589us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 341.720s 4556.244us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3260.250s 19616.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 166.330s 3207.357us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 320.260s 5074.422us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 71.760s 2637.938us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 145.380s 3065.472us 1 1 100.00
chip_sw_otp_ctrl_descrambling 197.120s 3436.151us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 201.100s 3550.477us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.510s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 184.220s 2886.598us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33230) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 47097749594173736381448316111248886888836187123720875234657008415840824020983 214
UVM_ERROR @ 2839.630971 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33230) { a_addr: 'h105bc a_data: 'h57acc16b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h18639 d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2839.630971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 15779845685360667860847129080826693484988833677043301019561415926903551166651 244
UVM_ERROR @ 7457.022755 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105b8 read out mismatch
UVM_INFO @ 7457.022755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31556) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 2969030978287034915050981590636809576503380669017522776967401943340604780288 221
UVM_ERROR @ 2190.673020 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31556) { a_addr: 'h106d4 a_data: 'h65d5af7c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h1aed8 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2190.673020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 82039377970910798116710344034529258623409859113989560675124875584357026578310 406
UVM_ERROR @ 3040.152194 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3040.152194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 4988494951225501524252434729483901263151651775454742317230898176738925614939 429
UVM_ERROR @ 6183.569360 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 6183.569360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 29080461134765677040349743334607968771951453711940006102957704050043065843824 398
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2755.775132 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2755.775132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 97686702539819398720542984904706945967513390937846169778805484105229283051300 400
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3027.047024 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3027.047024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 26086399844999367236523209431425241362141999482743599345077125389660129474853 418
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 86408618009879095619941663328244338865956457113547163256886482354537041177926 409
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 59401298336379455291941719225982602576213978240771902635961958377625723607061 426
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 94116917116821454691811570017546724171323012707228735426706599510340075983643 427
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 92308487232256931639785792462905587982232731236122188819174619240151338454823 428
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 22126649838933731663154540348529023488513280832275911585077470086852373360271 421
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 62475482695934752527353489513952563786887963195836909951263758848455358950253 417
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@77892) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 78543045619877202821231105957014302726666360561973915479794277568183412179308 428
UVM_ERROR @ 3458.447000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@77892) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3458.447000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 72027072994660101808585579621017128100988502302740635267412123805968281739741 425
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 11707.909000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11707.909000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 5532903089937589407422315968002175311193172065432691056541058782637538416885 405
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7016.908000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7016.908000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 21173032215978217257993533774153962058032914547445608058969889659388150708330 448
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 16106.066500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 16106.066500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 101180776584920639174852512157102590439981469870800471485097651743174365549024 412
UVM_ERROR @ 34789.849379 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34789.849379 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *!
chip_sw_alert_test 28525540124172243060724986278690476420126246640064000816112715877589099239754 390
UVM_ERROR @ 2806.255451 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
UVM_INFO @ 2806.255451 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 102148400592177468139945606030545494474219091639427025622691663526367930291754 396
UVM_ERROR @ 2610.267252 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2610.267252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 91351803438108453188475137332070176355208056022726184450951945306259252533325 None
Job timed out after 240 minutes
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 42534586237157371274641285629571285924768160731305944939572532609967272779320 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.164s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 54234693656674160690955703253016304576671492362663235605256432751711721313829 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.169s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 71395345802835605867015276840649376366254802626378892957303383669286307486234 410
UVM_FATAL @ 2600.681854 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2600.681854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 47915532478985251205846685886918331191421388011994859976604448901578766558847 395
UVM_ERROR @ 3090.410000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3090.410000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 24528274466296404007641568753725183666042580456802624864715281779723396708101 407
UVM_ERROR @ 2879.660000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 2879.660000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 39922849159372921144386191811905505269915990348611607261419499663959224134429 410
UVM_ERROR @ 16612.628736 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 16612.628736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 38443548343824810779527341446972956926636558726753720152467199482410528912857 502
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 7916560867302276233250280914221253294351642660412365806510279812156482145230 506
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 102201292907833371659534408884769056477672511517795744262291862249523259459075 494
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 105045694043377163463353369679480629264553333479916233905214721960413328948103 477
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 11241380925536807426112212667792767886993760921778754169632571852636565482190 500
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 14087516327013811003994185842456231488797272332039372550600458717183772730865 511
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 22985105632889521227443319853180748974846708741524685950522771178313309432957 509
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 11839298526707643004932636476797336003968961828855433973033528091281947323400 523
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 56464174087135627739514556407567936391136880876773955938289707655996923258454 514
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 83838807037811171306767533870466175124940503108728530508751920109507553927416 503
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 83295506266907987106332564503933825987743617478400433822704372034386984493743 546
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 18160122352482115151130750200587792763774426323634143519916967130237843475810 575
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 73054488657629327544584426212967842186003211803092247514853588528095284828993 562
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 29336243170411880105603569454501929661140261262399900367070874697951342217299 475
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16548038611678536954193724290324049139929987381148115467808935437817722823338 485
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 62090891286159744030386589569478870755176932861339996004642325953451793777228 445
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 48705155806606691805214603487530399286732474742620850263325059062917382499705 534
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 74880668732407121429087310084902630069600662452147778904616774737323958150049 492
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 63348025053582055042823778977998132338241223276346768932880470570013055449277 562
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 113516015737283926869846100672960469464630590044955839936613191424565041534590 491
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 97188611136250122654935606010551308656570266481458950816918722069874425288931 491
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 53539375567928872126837082293910808324491857448747298388207940950319919412299 481
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 99323537004778730421260599010418418227157727672104359132517216758960536287119 485
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 22004245895143694059105979259318836926000062178393094294491899212208443648188 491
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 58889183708110093437032837738657874703981351626372925631323029561937700295629 498
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_test_unlocked0 54284532244038658046008552692383860420927529655661583504007168591704699711159 428
UVM_ERROR @ 3643.099275 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
UVM_INFO @ 3643.099275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 3433206746504953796248026034497420146802616808431512571858546175351344971682 417
UVM_ERROR @ 16547.462648 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16547.462648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 59867013039928626772350819822781794691692754264280454722956292857405317643904 420
UVM_ERROR @ 17710.578416 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 17710.578416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---