Simulation Results: clkmgr

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.60 %
  • code
  • 98.57 %
  • assert
  • 95.62 %
  • func
  • 86.62 %
  • line
  • 99.22 %
  • branch
  • 98.96 %
  • cond
  • 94.67 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.24%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.930s 124.042us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.780s 42.361us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.730s 23.895us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.550s 750.827us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.660s 421.517us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.390s 60.531us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.730s 23.895us 1 1 100.00
clkmgr_csr_aliasing 1.660s 421.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.650s 19.665us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.670s 17.327us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.750s 25.979us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.700s 38.672us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.930s 124.042us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 4.490s 1551.127us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 8.220s 1817.604us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 4.490s 1551.127us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 35.330s 7612.176us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.780s 72.624us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.440s 107.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.440s 107.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 42.361us 1 1 100.00
clkmgr_csr_rw 0.730s 23.895us 1 1 100.00
clkmgr_csr_aliasing 1.660s 421.517us 1 1 100.00
clkmgr_same_csr_outstanding 0.890s 51.006us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 42.361us 1 1 100.00
clkmgr_csr_rw 0.730s 23.895us 1 1 100.00
clkmgr_csr_aliasing 1.660s 421.517us 1 1 100.00
clkmgr_same_csr_outstanding 0.890s 51.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 3.860s 1344.866us 1 1 100.00
clkmgr_tl_intg_err 2.100s 230.328us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.780s 282.415us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.780s 282.415us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.780s 282.415us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.780s 282.415us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.770s 299.528us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.100s 230.328us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 4.490s 1551.127us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 8.220s 1817.604us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.780s 282.415us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.820s 30.139us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.690s 19.951us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.770s 59.013us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 0 1 0.00
clkmgr_clk_handshake_intersig_mubi 0.590s 9.210us 0 1 0.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.710s 40.089us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.730s 23.895us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.860s 1344.866us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.730s 23.895us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.730s 23.895us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.860s 1344.866us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.730s 551.804us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 59.620s 19092.298us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 98687206761067109728046718631780490998984308816474431243819773441246503056678 71
UVM_ERROR @ 9209770 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (3 [0x3] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 9209770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---