Simulation Results: edn

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.91 %
  • code
  • 80.09 %
  • assert
  • 95.66 %
  • func
  • 78.97 %
  • line
  • 97.28 %
  • branch
  • 90.79 %
  • cond
  • 84.74 %
  • toggle
  • 78.71 %
  • FSM
  • 48.92 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.950s 48.620us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.140s 44.312us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.880s 60.072us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.880s 60.454us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 110.589us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.690s 35.404us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.880s 60.072us 1 1 100.00
edn_csr_aliasing 1.080s 110.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 114.047us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 114.047us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 114.047us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.090s 20.006us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.080s 32.941us 1 1 100.00
errs 1 1 100.00
edn_err 0.970s 25.575us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 14.184us 1 1 100.00
edn_disable_auto_req_mode 0.840s 178.099us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.290s 469.910us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.050s 17.413us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 33.096us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.880s 238.831us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.880s 238.831us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.140s 44.312us 1 1 100.00
edn_csr_rw 0.880s 60.072us 1 1 100.00
edn_csr_aliasing 1.080s 110.589us 1 1 100.00
edn_same_csr_outstanding 0.890s 44.185us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.140s 44.312us 1 1 100.00
edn_csr_rw 0.880s 60.072us 1 1 100.00
edn_csr_aliasing 1.080s 110.589us 1 1 100.00
edn_same_csr_outstanding 0.890s 44.185us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.500s 234.211us 1 1 100.00
edn_sec_cm 8.590s 5225.546us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 28.271us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.080s 32.941us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.590s 5225.546us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.590s 5225.546us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 8.590s 5225.546us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 8.590s 5225.546us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.080s 32.941us 1 1 100.00
edn_sec_cm 8.590s 5225.546us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.080s 32.941us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.500s 234.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 47.050s 12530.782us 1 1 100.00

Error Messages

   Test seed line log context