Simulation Results: edn

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.88 %
  • code
  • 81.08 %
  • assert
  • 97.14 %
  • func
  • 79.41 %
  • line
  • 97.72 %
  • branch
  • 92.21 %
  • cond
  • 89.23 %
  • toggle
  • 87.61 %
  • FSM
  • 38.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.050s 28.833us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 17.232us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 39.146us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.180s 259.643us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 41.189us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.170s 104.594us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 39.146us 1 1 100.00
edn_csr_aliasing 1.150s 41.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.380s 44.643us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.380s 44.643us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.380s 44.643us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 52.376us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.200s 100.824us 1 1 100.00
errs 1 1 100.00
edn_err 0.970s 59.282us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 29.273us 1 1 100.00
edn_disable_auto_req_mode 1.320s 49.633us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.060s 496.846us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.900s 41.023us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 43.781us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.120s 142.172us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.120s 142.172us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.090s 17.232us 1 1 100.00
edn_csr_rw 0.840s 39.146us 1 1 100.00
edn_csr_aliasing 1.150s 41.189us 1 1 100.00
edn_same_csr_outstanding 1.040s 53.625us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.090s 17.232us 1 1 100.00
edn_csr_rw 0.840s 39.146us 1 1 100.00
edn_csr_aliasing 1.150s 41.189us 1 1 100.00
edn_same_csr_outstanding 1.040s 53.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.050s 151.601us 1 1 100.00
edn_sec_cm 3.860s 312.419us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.130s 27.744us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.200s 100.824us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.860s 312.419us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.860s 312.419us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.860s 312.419us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.860s 312.419us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.200s 100.824us 1 1 100.00
edn_sec_cm 3.860s 312.419us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.200s 100.824us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.050s 151.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 43.040s 2647.365us 1 1 100.00

Error Messages

   Test seed line log context