Simulation Results: flash_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.65 %
  • code
  • 94.08 %
  • assert
  • 96.62 %
  • func
  • 96.26 %
  • line
  • 95.91 %
  • branch
  • 97.08 %
  • cond
  • 93.48 %
  • toggle
  • 98.21 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
98.46%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 32.810s 33.791us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.620s 17.477us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 12.650s 21.197us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.610s 27.754us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 26.930s 1148.491us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 24.930s 2185.066us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.500s 238.871us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.610s 27.754us 1 1 100.00
flash_ctrl_csr_aliasing 24.930s 2185.066us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.810s 67.197us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.450s 19.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.330s 94.777us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 43.660s 246.247us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1187.680s 85394.535us 1 1 100.00
flash_ctrl_hw_rma_reset 520.910s 90145.660us 1 1 100.00
flash_ctrl_lcmgr_intg 5.360s 39.881us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1715.390s 256788.487us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 123.720s 740.692us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 122.030s 10695.672us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1825.370s 131956.151us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 68.050s 1469.015us 1 1 100.00
rd_buff_eviction_w_ecc 2 3 66.67
flash_ctrl_rw_evict 16.520s 10.222us 0 1 0.00
flash_ctrl_rw_evict_all_en 17.550s 28.435us 1 1 100.00
flash_ctrl_re_evict 17.500s 104.012us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 77.500s 1373.191us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 77.500s 1373.191us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 95.700s 65635.385us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.410s 1184.490us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 235.720s 343.908us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 507.730s 6163.511us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 307.680s 1548.604us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 908.270s 529.974us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.740s 76.585us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 132.640s 2776.028us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.350s 30.722us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.750s 74.270us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 236.810s 326.812us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 116.440s 37134.076us 1 1 100.00
flash_ctrl_otp_reset 43.370s 67.011us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1187.680s 85394.535us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 81.610s 779.535us 1 1 100.00
flash_ctrl_intr_wr 60.140s 3073.959us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 144.890s 11938.998us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 180.450s 96576.654us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 37.240s 1811.150us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 33.280s 2576.618us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.000s 25.576us 1 1 100.00
flash_ctrl_ro_derr 116.160s 9193.936us 1 1 100.00
flash_ctrl_rw_derr 176.160s 4279.146us 1 1 100.00
flash_ctrl_derr_detect 121.400s 1732.573us 1 1 100.00
flash_ctrl_integrity 379.900s 17767.673us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.390s 128.245us 1 1 100.00
flash_ctrl_ro_serr 80.440s 1190.247us 1 1 100.00
flash_ctrl_rw_serr 125.200s 6196.521us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 43.110s 611.107us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 50.210s 955.840us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 169.880s 5989.544us 1 1 100.00
flash_ctrl_write_word_sweep 13.890s 203.294us 1 1 100.00
flash_ctrl_read_word_sweep 6.950s 26.036us 1 1 100.00
flash_ctrl_ro 73.380s 688.524us 1 1 100.00
flash_ctrl_rw 361.340s 16839.901us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.020s 624.723us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 739.400s 165755.313us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 27.840s 10064.451us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.670s 34.375us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.080s 25.429us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.720s 181.199us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.720s 181.199us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.650s 21.197us 1 1 100.00
flash_ctrl_csr_rw 8.610s 27.754us 1 1 100.00
flash_ctrl_csr_aliasing 24.930s 2185.066us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.670s 243.651us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.650s 21.197us 1 1 100.00
flash_ctrl_csr_rw 8.610s 27.754us 1 1 100.00
flash_ctrl_csr_aliasing 24.930s 2185.066us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.670s 243.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 25.030s 74.299us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 25.030s 74.299us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 25.030s 74.299us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 25.030s 74.299us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 26.700s 324.211us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 354.660s 735.900us 1 1 100.00
flash_ctrl_sec_cm 1545.980s 2758.544us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 354.660s 735.900us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 354.660s 735.900us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 20.020s 70.281us 1 1 100.00
flash_ctrl_wr_intg 6.980s 164.190us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 32.810s 33.791us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 43.370s 67.011us 1 1 100.00
flash_ctrl_disable 10.350s 30.722us 1 1 100.00
flash_ctrl_sec_info_access 39.790s 3799.951us 1 1 100.00
flash_ctrl_connect 6.750s 74.270us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.660s 59.479us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.610s 27.754us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.030s 74.299us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.610s 27.754us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.030s 74.299us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.610s 27.754us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.030s 74.299us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.350s 30.722us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 20.020s 70.281us 1 1 100.00
flash_ctrl_access_after_disable 8.960s 20.130us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.830s 27.227us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.350s 30.722us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.410s 1184.490us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 361.340s 16839.901us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 125.200s 6196.521us 1 1 100.00
flash_ctrl_rw_derr 176.160s 4279.146us 1 1 100.00
flash_ctrl_integrity 379.900s 17767.673us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1187.680s 85394.535us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1545.980s 2758.544us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1545.980s 2758.544us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1545.980s 2758.544us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1545.980s 2758.544us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 12.990s 681.677us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.670s 100.655us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 9.820s 48.877us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1545.980s 2758.544us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1545.980s 2758.544us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1545.980s 2758.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 17.760s 31.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 115.870s 174.342us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: *
flash_ctrl_rw_evict 94672648947982911027309368390373934944042946567821479977681856718264405534949 105
UVM_ERROR @ 10222.2 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 10222.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---