Simulation Results: hmac

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.36 %
  • code
  • 97.11 %
  • assert
  • 96.42 %
  • func
  • 44.55 %
  • line
  • 99.68 %
  • branch
  • 98.84 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.000s 1074.648us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.800s 44.671us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.830s 12.205us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.590s 8142.822us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.150s 2312.783us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.960s 91.824us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.830s 12.205us 1 1 100.00
hmac_csr_aliasing 4.150s 2312.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 36.530s 3943.171us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 35.060s 3747.193us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 202.560s 6241.334us 1 1 100.00
hmac_test_sha384_vectors 19.150s 255.884us 1 1 100.00
hmac_test_sha512_vectors 447.480s 15069.760us 1 1 100.00
hmac_test_hmac256_vectors 6.070s 393.923us 1 1 100.00
hmac_test_hmac384_vectors 8.260s 509.644us 1 1 100.00
hmac_test_hmac512_vectors 8.070s 781.158us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 14.810s 4570.341us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 68.110s 7485.449us 1 1 100.00
error 1 1 100.00
hmac_error 38.370s 3847.943us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 69.670s 14628.515us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.000s 1074.648us 1 1 100.00
hmac_long_msg 36.530s 3943.171us 1 1 100.00
hmac_back_pressure 35.060s 3747.193us 1 1 100.00
hmac_datapath_stress 68.110s 7485.449us 1 1 100.00
hmac_burst_wr 14.810s 4570.341us 1 1 100.00
hmac_stress_all 1176.110s 13562.248us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.000s 1074.648us 1 1 100.00
hmac_long_msg 36.530s 3943.171us 1 1 100.00
hmac_back_pressure 35.060s 3747.193us 1 1 100.00
hmac_datapath_stress 68.110s 7485.449us 1 1 100.00
hmac_wipe_secret 69.670s 14628.515us 1 1 100.00
hmac_test_sha256_vectors 202.560s 6241.334us 1 1 100.00
hmac_test_sha384_vectors 19.150s 255.884us 1 1 100.00
hmac_test_sha512_vectors 447.480s 15069.760us 1 1 100.00
hmac_test_hmac256_vectors 6.070s 393.923us 1 1 100.00
hmac_test_hmac384_vectors 8.260s 509.644us 1 1 100.00
hmac_test_hmac512_vectors 8.070s 781.158us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.000s 1074.648us 1 1 100.00
hmac_long_msg 36.530s 3943.171us 1 1 100.00
hmac_back_pressure 35.060s 3747.193us 1 1 100.00
hmac_datapath_stress 68.110s 7485.449us 1 1 100.00
hmac_burst_wr 14.810s 4570.341us 1 1 100.00
hmac_error 38.370s 3847.943us 1 1 100.00
hmac_wipe_secret 69.670s 14628.515us 1 1 100.00
hmac_test_sha256_vectors 202.560s 6241.334us 1 1 100.00
hmac_test_sha384_vectors 19.150s 255.884us 1 1 100.00
hmac_test_sha512_vectors 447.480s 15069.760us 1 1 100.00
hmac_test_hmac256_vectors 6.070s 393.923us 1 1 100.00
hmac_test_hmac384_vectors 8.260s 509.644us 1 1 100.00
hmac_test_hmac512_vectors 8.070s 781.158us 1 1 100.00
hmac_stress_all 1176.110s 13562.248us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1176.110s 13562.248us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.550s 11.416us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.620s 13.552us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.200s 540.910us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.200s 540.910us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.800s 44.671us 1 1 100.00
hmac_csr_rw 0.830s 12.205us 1 1 100.00
hmac_csr_aliasing 4.150s 2312.783us 1 1 100.00
hmac_same_csr_outstanding 1.040s 200.906us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.800s 44.671us 1 1 100.00
hmac_csr_rw 0.830s 12.205us 1 1 100.00
hmac_csr_aliasing 4.150s 2312.783us 1 1 100.00
hmac_same_csr_outstanding 1.040s 200.906us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.870s 288.297us 1 1 100.00
hmac_tl_intg_err 2.790s 692.051us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.790s 692.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.000s 1074.648us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.790s 131.912us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 54.700s 3464.821us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.830s 45.316us 1 1 100.00

Error Messages

   Test seed line log context