Simulation Results: i2c

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.75 %
  • code
  • 82.57 %
  • assert
  • 96.19 %
  • func
  • 81.50 %
  • line
  • 96.72 %
  • branch
  • 93.04 %
  • cond
  • 87.60 %
  • toggle
  • 89.66 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
93.88%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 23.070s 3585.039us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 7.620s 1646.425us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.830s 21.482us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.720s 40.161us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.380s 711.404us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.490s 1621.973us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.850s 121.087us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.720s 40.161us 1 1 100.00
i2c_csr_aliasing 1.490s 1621.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 0.960s 222.720us 1 1 100.00
host_stress_all 1 1 100.00
i2c_host_stress_all 564.340s 58522.435us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 438.260s 48835.063us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.880s 171.847us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 85.540s 5295.499us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 64.280s 1531.756us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.100s 178.082us 1 1 100.00
i2c_host_fifo_fmt_empty 6.100s 1615.155us 1 1 100.00
i2c_host_fifo_reset_rx 1.900s 116.843us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 76.100s 9725.015us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 9.180s 11910.498us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 2.760s 112.435us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.150s 528.320us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 29.410s 44707.601us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.260s 444.798us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 18.260s 672.958us 1 1 100.00
i2c_target_intr_smoke 3.960s 1124.821us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.600s 932.261us 1 1 100.00
i2c_target_fifo_reset_tx 1.060s 336.408us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 23.120s 41631.091us 1 1 100.00
i2c_target_stress_rd 18.260s 672.958us 1 1 100.00
i2c_target_intr_stress_wr 9.500s 9208.099us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.140s 1381.146us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 16.430s 3295.800us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.040s 821.704us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 4.610s 10072.847us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.260s 515.973us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.110s 94.453us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 438.260s 48835.063us 1 1 100.00
i2c_host_perf_precise 129.090s 6193.421us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 9.180s 11910.498us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.660s 71.664us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.900s 6479.899us 1 1 100.00
i2c_target_nack_acqfull_addr 2.010s 938.784us 1 1 100.00
i2c_target_nack_txstretch 1.250s 195.895us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 12.920s 568.644us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.770s 513.402us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.590s 18.575us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.720s 18.254us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.700s 95.415us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.700s 95.415us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.830s 21.482us 1 1 100.00
i2c_csr_rw 0.720s 40.161us 1 1 100.00
i2c_csr_aliasing 1.490s 1621.973us 1 1 100.00
i2c_same_csr_outstanding 0.930s 77.970us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.830s 21.482us 1 1 100.00
i2c_csr_rw 0.720s 40.161us 1 1 100.00
i2c_csr_aliasing 1.490s 1621.973us 1 1 100.00
i2c_same_csr_outstanding 0.930s 77.970us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.580s 296.410us 1 1 100.00
i2c_sec_cm 0.940s 323.062us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.580s 296.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 9.970s 1730.475us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.980s 72.789us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 2.910s 194.042us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 87933008225992942781083030865454406666798434828371945213705942217210751950188 81
UVM_ERROR @ 528320178 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 528320178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 19571942902423770445648338720186103654135692999370336183980093633008373397733 75
UVM_ERROR @ 72788717 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 187 [0xbb])
UVM_INFO @ 72788717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 95331307429358834151673182588191378451612222233782145472553514937145785150347 76
UVM_FATAL @ 10072846558 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10072846558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 27331405903045350460715020934162390538156701110268453713444342010455864123620 96
UVM_ERROR @ 1730474788 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1730474788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_target_stress_all_with_rand_reset 56948627686534879863220194314307953646539290214582706678584404614855928902638 84
UVM_ERROR @ 194042181 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 194042181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
i2c_host_mode_toggle 32620090689155505225145638936744574589977809968128273414223786811596753401944 84
UVM_ERROR @ 112435395 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
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