Simulation Results: kmac

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.31 %
  • code
  • 89.24 %
  • assert
  • 97.74 %
  • func
  • 92.95 %
  • line
  • 97.37 %
  • branch
  • 95.73 %
  • cond
  • 93.66 %
  • toggle
  • 99.92 %
  • FSM
  • 59.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 35.120s 3703.960us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.040s 113.274us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.850s 75.896us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.670s 995.243us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 6.170s 1729.781us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.790s 60.498us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.850s 75.896us 1 1 100.00
kmac_csr_aliasing 6.170s 1729.781us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.690s 24.891us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.040s 20.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1654.770s 63198.565us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 192.500s 11856.297us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1450.820s 60441.379us 1 1 100.00
kmac_test_vectors_sha3_256 1508.220s 59593.454us 1 1 100.00
kmac_test_vectors_sha3_384 1107.530s 221006.351us 1 1 100.00
kmac_test_vectors_sha3_512 716.520s 32517.299us 1 1 100.00
kmac_test_vectors_shake_128 1776.790s 254124.010us 1 1 100.00
kmac_test_vectors_shake_256 85.610s 39859.314us 1 1 100.00
kmac_test_vectors_kmac 1.800s 36.323us 1 1 100.00
kmac_test_vectors_kmac_xof 1.500s 29.534us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 266.380s 5716.276us 1 1 100.00
app 1 1 100.00
kmac_app 188.800s 45292.584us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 129.560s 9466.616us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 65.220s 10814.964us 1 1 100.00
error 1 1 100.00
kmac_error 227.730s 4192.899us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 5.990s 725.454us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 2.710s 116.398us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 3.180s 345.670us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 22.700s 1375.902us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 30.430s 10024.511us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.280s 108.946us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 450.160s 87131.628us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.680s 23.425us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.110s 18.052us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.930s 394.270us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.930s 394.270us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.040s 113.274us 1 1 100.00
kmac_csr_rw 0.850s 75.896us 1 1 100.00
kmac_csr_aliasing 6.170s 1729.781us 1 1 100.00
kmac_same_csr_outstanding 2.000s 354.515us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.040s 113.274us 1 1 100.00
kmac_csr_rw 0.850s 75.896us 1 1 100.00
kmac_csr_aliasing 6.170s 1729.781us 1 1 100.00
kmac_same_csr_outstanding 2.000s 354.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 95.604us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.180s 95.604us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 95.604us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.180s 95.604us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
kmac_shadow_reg_errors_with_csr_rw 1.420s 44.158us 0 1 0.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.810s 377.667us 1 1 100.00
kmac_sec_cm 18.680s 1648.601us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.810s 377.667us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.280s 108.946us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 35.120s 3703.960us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 266.380s 5716.276us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.180s 95.604us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 18.680s 1648.601us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 18.680s 1648.601us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 18.680s 1648.601us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 35.120s 3703.960us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.280s 108.946us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 18.680s 1648.601us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 232.910s 56565.258us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 35.120s 3703.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 144.690s 20441.176us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 7296460417069299839182092003934630036406710303370602356714702992119617782944 204
UVM_ERROR @ 44158276 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1473306239 [0x57d0de7f] vs 0 [0x0]) Regname: kmac_reg_block.prefix_6 reset value: 0x0
UVM_INFO @ 44158276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---