Simulation Results: lc_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.43 %
  • code
  • 82.74 %
  • assert
  • 94.13 %
  • func
  • 85.41 %
  • line
  • 97.04 %
  • branch
  • 93.51 %
  • cond
  • 79.03 %
  • toggle
  • 73.91 %
  • FSM
  • 70.21 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.390s 79.726us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.940s 49.743us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.910s 20.702us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.360s 96.794us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 33.731us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.130s 55.876us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.910s 20.702us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 33.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.230s 25.935us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.240s 227.177us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.880s 13.899us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.430s 113.113us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.220s 1374.461us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_prog_failure 1.430s 113.113us 1 1 100.00
lc_ctrl_errors 4.220s 1374.461us 1 1 100.00
lc_ctrl_security_escalation 6.290s 1951.613us 1 1 100.00
lc_ctrl_jtag_state_failure 1.940s 185.066us 0 1 0.00
lc_ctrl_jtag_prog_failure 1.940s 388.327us 1 1 100.00
lc_ctrl_jtag_errors 22.980s 3941.375us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 4.140s 906.091us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.120s 67.004us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 28.070s 8303.740us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.970s 426.263us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.850s 26.637us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.270s 151.628us 1 1 100.00
lc_ctrl_jtag_alert_test 1.720s 64.093us 1 1 100.00
lc_ctrl_jtag_smoke 2.400s 499.398us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.520s 105.777us 0 1 0.00
lc_ctrl_jtag_prog_failure 1.940s 388.327us 1 1 100.00
lc_ctrl_jtag_errors 22.980s 3941.375us 1 1 100.00
lc_ctrl_jtag_access 5.610s 1825.301us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 24.990s 10766.403us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.160s 1606.956us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.050s 31.292us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 36.790s 2670.762us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.040s 23.618us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.050s 172.832us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.050s 172.832us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.940s 49.743us 1 1 100.00
lc_ctrl_csr_rw 0.910s 20.702us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 33.731us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 40.615us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.940s 49.743us 1 1 100.00
lc_ctrl_csr_rw 0.910s 20.702us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 33.731us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 40.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.310s 1050.799us 1 1 100.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.310s 1050.799us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.240s 227.177us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.210s 9.126us 0 1 0.00
lc_ctrl_sec_cm 7.590s 244.471us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.290s 1951.613us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.230s 25.935us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3.520s 105.777us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.030s 704.997us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.030s 704.997us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.960s 1123.445us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.270s 958.349us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.270s 958.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 18.840s 1424.244us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 38012858990220483470927601457596883667458210074182345967006223322505898484638 171
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 9125995 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 9125995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 111473758925404604226601726915059724089177506642600871258070502341454024482683 167
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 25935363 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 25935363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 34828022471531257973506100948971722650275933653812796238718715957048820224971 194
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 185065955 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 185065955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 76512245485226328234638512121364058298112997341276131165247957014334703455183 284
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 105776634 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 105776634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 69868476245065342514334406335532293642663910449425328716891901360029313816794 3156
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2670761910 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2670761910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22595954964827438511221711158598056715712062444485007370159767513870200558021 808
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1424243883 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1424243883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---