Simulation Results: lc_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.72 %
  • code
  • 84.81 %
  • assert
  • 94.13 %
  • func
  • 90.21 %
  • line
  • 97.11 %
  • branch
  • 93.77 %
  • cond
  • 79.42 %
  • toggle
  • 81.10 %
  • FSM
  • 72.63 %
Validation stages
V1
100.00%
V2
92.50%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.260s 179.521us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.770s 17.184us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.860s 14.892us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.300s 216.668us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 21.756us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.900s 147.524us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.860s 14.892us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 21.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.340s 151.691us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.190s 201.237us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 18.475us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.580s 15.809us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.220s 965.413us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_prog_failure 1.580s 15.809us 1 1 100.00
lc_ctrl_errors 10.220s 965.413us 1 1 100.00
lc_ctrl_security_escalation 4.010s 242.643us 1 1 100.00
lc_ctrl_jtag_state_failure 7.030s 267.858us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.480s 1827.134us 1 1 100.00
lc_ctrl_jtag_errors 51.950s 2930.858us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.320s 59.510us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.290s 205.426us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.760s 4003.916us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.360s 1446.140us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.920s 47.349us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.610s 88.698us 1 1 100.00
lc_ctrl_jtag_alert_test 1.130s 44.770us 1 1 100.00
lc_ctrl_jtag_smoke 3.180s 386.555us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.120s 439.151us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.480s 1827.134us 1 1 100.00
lc_ctrl_jtag_errors 51.950s 2930.858us 1 1 100.00
lc_ctrl_jtag_access 10.900s 1280.771us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.090s 651.918us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.930s 922.957us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.930s 15.423us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 6.630s 181.163us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.070s 97.269us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.580s 34.984us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.580s 34.984us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 17.184us 1 1 100.00
lc_ctrl_csr_rw 0.860s 14.892us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 21.756us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 96.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 17.184us 1 1 100.00
lc_ctrl_csr_rw 0.860s 14.892us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 21.756us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 96.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.680s 173.660us 1 1 100.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.680s 173.660us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.190s 201.237us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.420s 184.196us 0 1 0.00
lc_ctrl_sec_cm 9.960s 246.779us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.010s 242.643us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.340s 151.691us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.120s 439.151us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.850s 1295.971us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.850s 1295.971us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.300s 1479.705us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.030s 454.039us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.030s 454.039us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 28.800s 5489.362us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 113166923928283940622102389870447210205370757625882021924127106802023145855411 667
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 184195970 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 184195970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 83599236276527044263385595311289575668852897405101837501408052920395259963908 633
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 267858020 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 267858020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43492528063782721490180640029714770950512963007911942374856685347341354734225 1950
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 5489361668 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 5489361668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---