| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
77.42% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 7.000s | 40.543us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 7.000s | 42.382us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 4.000s | 27.236us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 6.000s | 52.465us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 4.000s | 19.419us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 5.000s | 58.839us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 4.000s | 27.236us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 19.419us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 36.000s | 4959.455us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 10.000s | 910.185us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 28.000s | 371.464us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 36.000s | 833.887us | 1 | 1 | 100.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 76.000s | 300.120us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 26.000s | 380.944us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 5.000s | 49.224us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 5.000s | 60.070us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 18.000s | 120.346us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 4.000s | 19.133us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 3.000s | 22.526us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 5.000s | 33.545us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 5.000s | 33.545us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 7.000s | 42.382us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 27.236us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 19.419us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 3.000s | 90.232us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 7.000s | 42.382us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 27.236us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 19.419us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 3.000s | 90.232us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 5.000s | 27.906us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 10.000s | 55.237us | 1 | 1 | 100.00 | |
| internal_integrity | 4 | 4 | 100.00 | |||
| otbn_alu_bignum_mod_err | 13.000s | 96.359us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 7.000s | 284.931us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 5.000s | 17.477us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 5.000s | 17.212us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 10.000s | 47.344us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 5.000s | 23.218us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 5.000s | 20.192us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| otbn_tl_intg_err | 8.000s | 575.345us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 19.000s | 733.009us | 1 | 1 | 100.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 7.000s | 40.543us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 10.000s | 55.237us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 5.000s | 27.906us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 8.000s | 575.345us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 5.000s | 49.224us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 5.000s | 27.906us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 10.000s | 55.237us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 60.070us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 10.000s | 47.344us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_controller_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 5.000s | 27.906us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 10.000s | 55.237us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 60.070us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 10.000s | 47.344us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 5.000s | 49.224us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 5.000s | 27.906us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 10.000s | 55.237us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 60.070us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 10.000s | 47.344us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 8.000s | 29.025us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 6.000s | 15.495us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 13.000s | 332.368us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 13.000s | 332.368us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 7.000s | 80.831us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 11.000s | 73.368us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 8.000s | 23.188us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 8.000s | 23.188us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 3.000s | 45.811us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 76.000s | 300.120us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 11.000s | 47.696us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 5.000s | 47.530us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 12.000s | 58.715us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 433.000s | 1763.493us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| otbn_stress_all_with_rand_reset | 38107301755099461802039505463973996976774062325021337250494023367205512604724 | 382 |
UVM_ERROR @ 1763492935 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1763492935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed | ||||
| otbn_sec_cm | 40119133712314125465425442067378843506735858655855393558876297913128454536261 | 106 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 58715199 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 58715199 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 58715199 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 58715199 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 58715199 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
|
|