Simulation Results: otp_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.04 %
  • code
  • 78.75 %
  • assert
  • 93.78 %
  • func
  • 76.58 %
  • line
  • 88.24 %
  • branch
  • 83.07 %
  • cond
  • 90.02 %
  • toggle
  • 88.84 %
  • FSM
  • 43.58 %
Validation stages
V1
100.00%
V2
92.00%
V2S
94.64%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.460s 198.663us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.180s 3839.943us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.360s 71.181us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.350s 79.005us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.540s 1768.077us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.250s 66.165us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.080s 200.152us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.350s 79.005us 1 1 100.00
otp_ctrl_csr_aliasing 2.250s 66.165us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.070s 73.455us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.150s 134.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.950s 789.361us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.050s 509.293us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 5.220s 659.410us 0 1 0.00
otp_ctrl_check_fail 16.730s 10549.005us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 8.390s 4531.285us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 8.250s 2458.592us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 11.410s 805.953us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 3.770s 299.219us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 9.310s 770.891us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 7.120s 995.007us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 30.250s 13664.992us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 158.270s 20531.460us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.200s 520.972us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.470s 198.799us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.970s 244.757us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.970s 244.757us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.360s 71.181us 1 1 100.00
otp_ctrl_csr_rw 1.350s 79.005us 1 1 100.00
otp_ctrl_csr_aliasing 2.250s 66.165us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.940s 1094.137us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.360s 71.181us 1 1 100.00
otp_ctrl_csr_rw 1.350s 79.005us 1 1 100.00
otp_ctrl_csr_aliasing 2.250s 66.165us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.940s 1094.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
otp_ctrl_tl_intg_err 7.780s 690.354us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.780s 690.354us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.180s 3839.943us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.180s 3839.943us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
otp_ctrl_macro_errs 7.120s 995.007us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
otp_ctrl_macro_errs 7.120s 995.007us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.030s 440.211us 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.050s 509.293us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 16.730s 10549.005us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 8.250s 2458.592us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 8.250s 2458.592us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 8.250s 2458.592us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 8.250s 2458.592us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 8.250s 2458.592us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.180s 3839.943us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 8.250s 2458.592us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.180s 3839.943us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.360s 17317.392us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 8.390s 4531.285us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.180s 3839.943us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.180s 3839.943us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 7.120s 995.007us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.210s 3017.703us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.490s 54.772us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 92876470575164532728290318692504836030123053289213126053858127060208438406246 2842
UVM_ERROR @ 659410112 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 659410112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 79507643448466973402905920142038293998750198192211428253144382735786062325885 4124
UVM_ERROR @ 995007360 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4118372160 [0xf5795f40] vs 4118368064 [0xf5794f40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 995007360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 84899286877496539651777222284442687677862223946231256453949554403713955521479 98
UVM_ERROR @ 54771568 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54771568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---