pwrmgr Simulation Results

Simulation Results: pwrmgr

16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.75 %

code
94.45 %

assert
96.08 %

func
96.71 %

line
98.92 %

branch
95.42 %

cond
94.06 %

toggle
89.83 %

FSM
94.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		52.94%
V3		50.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	pwrmgr_smoke	0.630s	24.209us	1	1	100.00
csr_hw_reset				1	1	100.00
	pwrmgr_csr_hw_reset	0.580s	25.077us	1	1	100.00
csr_rw				1	1	100.00
	pwrmgr_csr_rw	0.600s	47.297us	1	1	100.00
csr_bit_bash				1	1	100.00
	pwrmgr_csr_bit_bash	1.290s	161.932us	1	1	100.00
csr_aliasing				1	1	100.00
	pwrmgr_csr_aliasing	0.760s	28.161us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	pwrmgr_csr_mem_rw_with_rand_reset	0.900s	98.012us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	pwrmgr_csr_rw	0.600s	47.297us	1	1	100.00
	pwrmgr_csr_aliasing	0.760s	28.161us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wakeup				1	1	100.00
	pwrmgr_wakeup	0.760s	185.671us	1	1	100.00
control_clks				1	1	100.00
	pwrmgr_wakeup	0.760s	185.671us	1	1	100.00
aborted_low_power				2	2	100.00
	pwrmgr_aborted_low_power	0.640s	21.154us	1	1	100.00
	pwrmgr_lowpower_invalid	0.680s	56.134us	1	1	100.00
reset				2	2	100.00
	pwrmgr_reset	0.670s	49.267us	1	1	100.00
	pwrmgr_reset_invalid	0.700s	124.779us	1	1	100.00
main_power_glitch_reset				1	1	100.00
	pwrmgr_reset	0.670s	49.267us	1	1	100.00
reset_wakeup_race				1	1	100.00
	pwrmgr_wakeup_reset	0.870s	236.430us	1	1	100.00
lowpower_wakeup_race				1	1	100.00
	pwrmgr_lowpower_wakeup_race	0.630s	49.397us	1	1	100.00
disable_rom_integrity_check				1	1	100.00
	pwrmgr_disable_rom_integrity_check	0.820s	80.859us	1	1	100.00
stress_all				0	1	0.00
	pwrmgr_stress_all	1.970s	11715.434us	0	1	0.00
intr_test				1	1	100.00
	pwrmgr_intr_test	0.590s	26.450us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	pwrmgr_tl_errors	1.070s	118.791us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	pwrmgr_tl_errors	1.070s	118.791us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.580s	25.077us	1	1	100.00
	pwrmgr_csr_rw	0.600s	47.297us	1	1	100.00
	pwrmgr_csr_aliasing	0.760s	28.161us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.810s	34.872us	1	1	100.00
tl_d_partial_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.580s	25.077us	1	1	100.00
	pwrmgr_csr_rw	0.600s	47.297us	1	1	100.00
	pwrmgr_csr_aliasing	0.760s	28.161us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.810s	34.872us	1	1	100.00

V2S

9/17 passed

52.94 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	2	0.00
	pwrmgr_sec_cm	0.660s	20.368us	0	1	0.00
	pwrmgr_tl_intg_err	0.590s	6.862us	0	1	0.00
prim_count_check				0	1	0.00
	pwrmgr_sec_cm	0.660s	20.368us	0	1	0.00
prim_fsm_check				0	1	0.00
	pwrmgr_sec_cm	0.660s	20.368us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	pwrmgr_tl_intg_err	0.590s	6.862us	0	1	0.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.830s	788.577us	1	1	100.00
sec_cm_rom_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_wakeup_reset	0.870s	236.430us	1	1	100.00
sec_cm_rstmgr_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.730s	66.542us	1	1	100.00
sec_cm_esc_rx_clk_bkgn_chk				1	1	100.00
	pwrmgr_esc_clk_rst_malfunc	0.570s	41.127us	1	1	100.00
sec_cm_esc_rx_clk_local_esc				0	1	0.00
	pwrmgr_sec_cm	0.660s	20.368us	0	1	0.00
sec_cm_fsm_sparse				0	1	0.00
	pwrmgr_sec_cm	0.660s	20.368us	0	1	0.00
sec_cm_fsm_terminal				0	1	0.00
	pwrmgr_sec_cm	0.660s	20.368us	0	1	0.00
sec_cm_ctrl_flow_global_esc				1	1	100.00
	pwrmgr_global_esc	0.570s	57.757us	1	1	100.00
sec_cm_main_pd_rst_local_esc				1	1	100.00
	pwrmgr_glitch	0.590s	54.614us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	pwrmgr_sec_cm_ctrl_config_regwen	0.640s	77.260us	1	1	100.00
sec_cm_wakeup_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.600s	47.297us	1	1	100.00
sec_cm_reset_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.600s	47.297us	1	1	100.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
escalation_timeout				0	1	0.00
	pwrmgr_escalation_timeout	0.720s	92.174us	0	1	0.00
stress_all_with_rand_reset				1	1	100.00
	pwrmgr_stress_all_with_rand_reset	9.240s	4464.301us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
	pwrmgr_escalation_timeout	24025186787976563856854547603678763845069050381148819154147310109842308339372	72	UVM_ERROR @ 92173585 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A UVM_INFO @ 92173585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
	pwrmgr_sec_cm	67258620144538739665709807596020664064237934399839393534809928670399111190734	76	UVM_ERROR @ 20368288 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 20368288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_tl_intg_err	98683790895358384542866402639767353919329287017534385031600904509437957110539	82	UVM_ERROR @ 6861991 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 6861991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
	pwrmgr_stress_all	90700187179527900306140640872539677332813957700686293707056021588350590359339	288	UVM_FATAL @ 11715433543 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred! UVM_INFO @ 11715433543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---