Simulation Results: rom_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.19 %
  • code
  • 96.90 %
  • assert
  • 95.34 %
  • func
  • 93.32 %
  • line
  • 99.32 %
  • branch
  • 98.54 %
  • cond
  • 94.06 %
  • toggle
  • 99.24 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.450s 1064.024us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.600s 568.660us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.130s 632.698us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.600s 172.425us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 129.824us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.120s 216.530us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.130s 632.698us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 129.824us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.620s 301.475us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.640s 130.270us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.880s 557.774us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 14.710s 6323.912us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.530s 298.417us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.050s 166.370us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.390s 275.501us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.390s 275.501us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.600s 568.660us 1 1 100.00
rom_ctrl_csr_rw 3.130s 632.698us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 129.824us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.690s 313.515us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.600s 568.660us 1 1 100.00
rom_ctrl_csr_rw 3.130s 632.698us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 129.824us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.690s 313.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.560s 603.613us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 98.760s 549.191us 0 1 0.00
rom_ctrl_tl_intg_err 23.080s 927.949us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 98.760s 549.191us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 98.760s 549.191us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 98.760s 549.191us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 98.760s 549.191us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.450s 1064.024us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.450s 1064.024us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.450s 1064.024us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.080s 927.949us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
rom_ctrl_kmac_err_chk 7.530s 298.417us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 42.890s 1871.223us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.560s 603.613us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 98.760s 549.191us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 81.050s 2924.459us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 6591802618455475721984037479362654459508707807490727826954970541119243450990 123
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 13537353ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 13537353ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 13537353ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))