Simulation Results: rom_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.35 %
  • code
  • 92.24 %
  • assert
  • 95.34 %
  • func
  • 95.47 %
  • line
  • 99.32 %
  • branch
  • 96.72 %
  • cond
  • 92.42 %
  • toggle
  • 99.39 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.770s 1538.299us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.240s 302.852us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 8.540s 218.542us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 10.120s 1161.123us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.940s 1110.876us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.960s 768.406us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 8.540s 218.542us 1 1 100.00
rom_ctrl_csr_aliasing 6.940s 1110.876us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.100s 372.206us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.520s 1068.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.970s 578.935us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 25.350s 739.482us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.460s 2029.218us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 8.870s 3813.450us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.920s 294.831us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.920s 294.831us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.240s 302.852us 1 1 100.00
rom_ctrl_csr_rw 8.540s 218.542us 1 1 100.00
rom_ctrl_csr_aliasing 6.940s 1110.876us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.970s 331.871us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.240s 302.852us 1 1 100.00
rom_ctrl_csr_rw 8.540s 218.542us 1 1 100.00
rom_ctrl_csr_aliasing 6.940s 1110.876us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.970s 331.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.960s 5731.082us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 227.580s 2124.929us 0 1 0.00
rom_ctrl_tl_intg_err 50.030s 1588.994us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 227.580s 2124.929us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 227.580s 2124.929us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 227.580s 2124.929us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 227.580s 2124.929us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.770s 1538.299us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.770s 1538.299us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.770s 1538.299us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 50.030s 1588.994us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
rom_ctrl_kmac_err_chk 14.460s 2029.218us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.750s 1658.148us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.960s 5731.082us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 227.580s 2124.929us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 56.130s 20691.603us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 88084107298542883680054735144804705621278981173907206765773085624897952337528 501
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 193388890ps failed at 193388890ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 193388890ps failed at 193388890ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'