Simulation Results: rv_timer

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.86 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 96.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.950s 118.199us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.540s 44.609us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.630s 51.865us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.150s 68.580us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.620s 33.371us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.890s 95.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.630s 51.865us 1 1 100.00
rv_timer_csr_aliasing 0.620s 33.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.870s 64.287us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.680s 1061.498us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 24.640s 42705.115us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 24.640s 42705.115us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.730s 6669.398us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.800s 16.383us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.530s 45.647us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.970s 33.240us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.970s 33.240us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.540s 44.609us 1 1 100.00
rv_timer_csr_rw 0.630s 51.865us 1 1 100.00
rv_timer_csr_aliasing 0.620s 33.371us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 78.050us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.540s 44.609us 1 1 100.00
rv_timer_csr_rw 0.630s 51.865us 1 1 100.00
rv_timer_csr_aliasing 0.620s 33.371us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 78.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_tl_intg_err 1.130s 114.572us 1 1 100.00
rv_timer_sec_cm 0.780s 137.997us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.130s 114.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.650s 38.947us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.700s 45.930us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 15.430s 9390.068us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 37530750269526185107011833781608838589141421874332714403278314985138090489599 72
UVM_ERROR @ 45929937 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45929937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 9729051297889309372667204141466748204918191779850728627331073035607099243215 72
UVM_FATAL @ 64286948 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xbb1b504) == 0x1
UVM_INFO @ 64286948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---