Simulation Results: spi_device

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.50 %
  • code
  • 93.97 %
  • assert
  • 94.27 %
  • func
  • 68.25 %
  • line
  • 99.10 %
  • branch
  • 98.28 %
  • cond
  • 95.54 %
  • toggle
  • 87.57 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 51.820s 12212.276us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.110s 23.142us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.140s 143.667us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.300s 704.456us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.560s 1265.924us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.010s 78.294us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.140s 143.667us 1 1 100.00
spi_device_csr_aliasing 15.560s 1265.924us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.850s 12.047us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.160s 29.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.840s 22.481us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.880s 14.796us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.680s 18.939us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.630s 18.323us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.630s 18.323us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.840s 596.915us 1 1 100.00
spi_device_tpm_sts_read 0.810s 347.393us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 7.240s 1117.250us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.850s 7148.756us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.860s 105.352us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.860s 105.352us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.550s 222.325us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.550s 222.325us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.550s 222.325us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.550s 222.325us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.550s 222.325us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.660s 2605.110us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.590s 59.397us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.590s 59.397us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.590s 59.397us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 24.400s 4896.058us 1 1 100.00
spi_device_read_buffer_direct 5.180s 876.457us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.590s 59.397us 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 105.680s 52698.727us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.980s 1442.779us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.980s 1442.779us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 51.820s 12212.276us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 249.230s 84649.129us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 100.390s 86149.019us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.730s 22.537us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.870s 15.537us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.730s 232.335us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.730s 232.335us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.110s 23.142us 1 1 100.00
spi_device_csr_rw 1.140s 143.667us 1 1 100.00
spi_device_csr_aliasing 15.560s 1265.924us 1 1 100.00
spi_device_same_csr_outstanding 2.290s 1841.126us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.110s 23.142us 1 1 100.00
spi_device_csr_rw 1.140s 143.667us 1 1 100.00
spi_device_csr_aliasing 15.560s 1265.924us 1 1 100.00
spi_device_same_csr_outstanding 2.290s 1841.126us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 10.410s 550.796us 1 1 100.00
spi_device_sec_cm 1.060s 152.355us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.410s 550.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 0.810s 45.637us 1 1 100.00

Error Messages

   Test seed line log context