Simulation Results: spi_host

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.24 %
  • code
  • 94.86 %
  • assert
  • 93.54 %
  • func
  • 88.33 %
  • block
  • 96.64 %
  • line
  • 98.47 %
  • branch
  • 92.95 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 34.000s 4641.305us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 4.000s 77.263us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 33.391us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 537.650us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 6.000s 37.918us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 73.060us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 33.391us 1 1 100.00
spi_host_csr_aliasing 6.000s 37.918us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 6.000s 37.684us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 4.000s 17.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 101.206us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 45.934us 1 1 100.00
spi_host_error_cmd 2.000s 45.427us 1 1 100.00
spi_host_event 8.000s 4159.501us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 50.080us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 50.080us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 50.080us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 6.000s 639.817us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 23.078us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 50.080us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 50.080us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 34.000s 4641.305us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 34.000s 4641.305us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 27.000s 6158.557us 1 1 100.00
spien 1 1 100.00
spi_host_spien 6.000s 2183.327us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 10.000s 4321.518us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 139.068us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 45.934us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 16.377us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 6.000s 43.850us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 7.000s 269.519us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 7.000s 269.519us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 4.000s 77.263us 1 1 100.00
spi_host_csr_rw 1.000s 33.391us 1 1 100.00
spi_host_csr_aliasing 6.000s 37.918us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 22.442us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 4.000s 77.263us 1 1 100.00
spi_host_csr_rw 1.000s 33.391us 1 1 100.00
spi_host_csr_aliasing 6.000s 37.918us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 22.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 7.000s 94.149us 1 1 100.00
spi_host_sec_cm 2.000s 177.266us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 7.000s 94.149us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 228.000s 39779.264us 1 1 100.00

Error Messages

   Test seed line log context