Simulation Results: sram_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.82 %
  • code
  • 95.90 %
  • assert
  • 95.83 %
  • func
  • 95.73 %
  • line
  • 99.11 %
  • branch
  • 97.52 %
  • cond
  • 92.17 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 14.650s 6337.828us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.780s 62.188us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.750s 28.715us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.190s 96.470us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.830s 17.881us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.380s 5654.141us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.750s 28.715us 1 1 100.00
sram_ctrl_csr_aliasing 0.830s 17.881us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 236.090s 197179.005us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 121.420s 12073.369us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 571.430s 10179.735us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 109.830s 2857.862us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 952.230s 47921.752us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 862.220s 279894.959us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 31.280s 8712.555us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 158.130s 11238.777us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 25.220s 2660.505us 1 1 100.00
sram_ctrl_partial_access_b2b 239.500s 12746.555us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 17.110s 7195.561us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.170s 2757.266us 1 1 100.00
sram_ctrl_throughput_w_readback 16.360s 3123.128us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 377.860s 13270.973us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.350s 691.236us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 3040.700s 263473.955us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.630s 75.043us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.830s 72.406us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.830s 72.406us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 62.188us 1 1 100.00
sram_ctrl_csr_rw 0.750s 28.715us 1 1 100.00
sram_ctrl_csr_aliasing 0.830s 17.881us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 16.260us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 62.188us 1 1 100.00
sram_ctrl_csr_rw 0.750s 28.715us 1 1 100.00
sram_ctrl_csr_aliasing 0.830s 17.881us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 16.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.540s 7500.782us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.840s 3.152us 0 1 0.00
sram_ctrl_tl_intg_err 1.330s 82.822us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.152us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.330s 82.822us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 377.860s 13270.973us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 377.860s 13270.973us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.750s 28.715us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 158.130s 11238.777us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 158.130s 11238.777us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 158.130s 11238.777us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 31.280s 8712.555us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.770s 1360.698us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.540s 7500.782us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.390s 1382.107us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 14.650s 6337.828us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 14.650s 6337.828us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 158.130s 11238.777us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.152us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 31.280s 8712.555us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.152us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.152us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 14.650s 6337.828us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.152us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 93.410s 3229.110us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 83019921175606102877344349097955224028949082536376233053479879286861995873725 97
UVM_ERROR @ 3151934 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3151934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---