Simulation Results: sram_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 95.90 %
  • assert
  • 95.65 %
  • func
  • 95.36 %
  • line
  • 99.07 %
  • branch
  • 97.47 %
  • cond
  • 92.29 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 23.910s 444.476us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.890s 15.020us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.760s 30.971us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.690s 256.651us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 14.879us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.110s 83.478us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.760s 30.971us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 14.879us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.800s 2398.095us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.920s 382.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 506.240s 20957.422us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 208.560s 2971.833us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 24.010s 8580.140us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 576.150s 20594.540us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 1.810s 95.259us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 54.350s 400.744us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.900s 855.526us 1 1 100.00
sram_ctrl_partial_access_b2b 222.330s 8323.648us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 32.600s 122.533us 1 1 100.00
sram_ctrl_throughput_w_partial_write 38.300s 2074.244us 1 1 100.00
sram_ctrl_throughput_w_readback 39.090s 1298.810us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 612.110s 94856.061us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.840s 29.298us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 447.640s 4443.261us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.860s 12.420us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.980s 158.950us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.980s 158.950us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.890s 15.020us 1 1 100.00
sram_ctrl_csr_rw 0.760s 30.971us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 14.879us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.910s 18.855us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.890s 15.020us 1 1 100.00
sram_ctrl_csr_rw 0.760s 30.971us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 14.879us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.910s 18.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.070s 805.724us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.890s 3.016us 0 1 0.00
sram_ctrl_tl_intg_err 1.940s 1469.493us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.890s 3.016us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.940s 1469.493us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 612.110s 94856.061us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 612.110s 94856.061us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.760s 30.971us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 54.350s 400.744us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 54.350s 400.744us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 54.350s 400.744us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 1.810s 95.259us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.160s 48.200us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.070s 805.724us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.960s 34.995us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 23.910s 444.476us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 23.910s 444.476us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 54.350s 400.744us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.890s 3.016us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 1.810s 95.259us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.890s 3.016us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.890s 3.016us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 23.910s 444.476us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.890s 3.016us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 24.270s 4883.446us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 83733695971067225537035345752900034759728633455275297724148328323906963882414 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 3015826 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3015826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---