Simulation Results: sysrst_ctrl

 
16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.40 %
  • code
  • 93.84 %
  • assert
  • 95.50 %
  • func
  • 72.87 %
  • line
  • 98.01 %
  • branch
  • 97.78 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.460s 2127.297us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.860s 2456.218us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.000s 2435.444us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.740s 2504.610us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.870s 6126.377us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.570s 2114.159us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 5.870s 3045.736us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.980s 3166.373us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.590s 2067.718us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.570s 2114.159us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.980s 3166.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 37.350s 88469.538us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 80.650s 82862.956us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.050s 3532.858us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.800s 3189.672us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.750s 2528.233us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.570s 2222.380us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.240s 3677.998us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.860s 2632.022us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.680s 4311.560us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 61.020s 32627.148us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 174.540s 192059.046us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.960s 2011.188us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.370s 2026.025us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.100s 2039.358us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.100s 2039.358us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.870s 6126.377us 1 1 100.00
sysrst_ctrl_csr_rw 1.570s 2114.159us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.980s 3166.373us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.710s 8141.449us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.870s 6126.377us 1 1 100.00
sysrst_ctrl_csr_rw 1.570s 2114.159us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.980s 3166.373us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.710s 8141.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 75.020s 42016.356us 1 1 100.00
sysrst_ctrl_tl_intg_err 82.340s 42455.296us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 82.340s 42455.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 15.410s 8196.388us 1 1 100.00

Error Messages

   Test seed line log context