uart Simulation Results

Simulation Results: uart

16/12/2025 19:25:10 sha: de081ff json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.87 %

code
96.19 %

assert
97.12 %

func
49.31 %

line
99.17 %

branch
97.20 %

cond
96.85 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		94.12%
V2S		100.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	10.620s	5551.413us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.730s	19.659us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.590s	18.897us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.100s	356.399us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.950s	103.407us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.670s	89.665us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.590s	18.897us	1	1	100.00
	uart_csr_aliasing	0.950s	103.407us	1	1	100.00

32/34 passed

94.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	8.410s	78851.174us	1	1	100.00
parity				2	2	100.00
	uart_smoke	10.620s	5551.413us	1	1	100.00
	uart_tx_rx	8.410s	78851.174us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	9.590s	37676.022us	1	1	100.00
	uart_rx_parity_err	107.000s	118366.697us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	8.410s	78851.174us	1	1	100.00
	uart_intr	9.590s	37676.022us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	300.560s	148854.622us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	20.770s	21611.753us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	11.210s	12199.392us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	9.590s	37676.022us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	9.590s	37676.022us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	9.590s	37676.022us	1	1	100.00
perf				1	1	100.00
	uart_perf	34.280s	3799.276us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	10.620s	7826.626us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	10.620s	7826.626us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	8.820s	5515.354us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	2.650s	4200.545us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	2.480s	3187.743us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	42.460s	6324.017us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	662.470s	178667.689us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	1.980s	3973.062us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	0.650s	18.621us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.800s	35.554us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.840s	655.560us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.840s	655.560us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.730s	19.659us	1	1	100.00
	uart_csr_rw	0.590s	18.897us	1	1	100.00
	uart_csr_aliasing	0.950s	103.407us	1	1	100.00
	uart_same_csr_outstanding	0.730s	113.670us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.730s	19.659us	1	1	100.00
	uart_csr_rw	0.590s	18.897us	1	1	100.00
	uart_csr_aliasing	0.950s	103.407us	1	1	100.00
	uart_same_csr_outstanding	0.730s	113.670us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_tl_intg_err	1.260s	971.655us	1	1	100.00
	uart_sec_cm	1.230s	99.816us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.260s	971.655us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	40.630s	3513.189us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:
	uart_noise_filter	113804559214110341308241314282449831414538328180335871981944861193570733451793	73	UVM_ERROR @ 4043001709 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 4043012018 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 4043022327 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (112 [0x70] vs 247 [0xf7]) reg name: uart_reg_block.rdata UVM_ERROR @ 4105113434 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 4105123743 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_stress_all	96304619827607673613534605556098460455415236224066749607196033314022448930427	73	UVM_ERROR @ 2329621971 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 2329661971 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2329861971 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (199 [0xc7] vs 253 [0xfd]) reg name: uart_reg_block.rdata UVM_ERROR @ 2572061971 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 2572101971 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty