Simulation Results: adc_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.14 %
  • code
  • 97.02 %
  • assert
  • 95.95 %
  • func
  • 47.46 %
  • line
  • 99.02 %
  • branch
  • 98.51 %
  • cond
  • 95.66 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.920s 6112.981us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.870s 1245.641us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.270s 455.951us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 13.540s 26435.407us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.140s 1002.712us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.080s 447.320us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.270s 455.951us 1 1 100.00
adc_ctrl_csr_aliasing 2.140s 1002.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 271.030s 163301.160us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 498.550s 326474.167us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 229.260s 498489.487us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 268.830s 325811.241us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 89.410s 226321.530us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 499.430s 600872.238us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 76.430s 162661.442us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 706.780s 533739.782us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.080s 4958.502us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 14.210s 29067.723us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 58.430s 109233.823us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 155.380s 193103.112us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.240s 501.531us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.020s 301.006us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.460s 482.447us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.460s 482.447us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.870s 1245.641us 1 1 100.00
adc_ctrl_csr_rw 1.270s 455.951us 1 1 100.00
adc_ctrl_csr_aliasing 2.140s 1002.712us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.160s 5249.892us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.870s 1245.641us 1 1 100.00
adc_ctrl_csr_rw 1.270s 455.951us 1 1 100.00
adc_ctrl_csr_aliasing 2.140s 1002.712us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.160s 5249.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 17.270s 8112.632us 1 1 100.00
adc_ctrl_sec_cm 9.370s 4500.037us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 17.270s 8112.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 6.210s 17010.735us 1 1 100.00

Error Messages

   Test seed line log context