Simulation Results: chip

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.50 %
  • code
  • 85.22 %
  • assert
  • 96.28 %
  • func
  • 44.99 %
  • line
  • 94.35 %
  • branch
  • 93.67 %
  • cond
  • 89.56 %
  • toggle
  • 91.39 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
86.76%
V2S
50.00%
V3
63.33%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 113.150s 2186.216us 1 1 100.00
chip_sw_example_rom 62.840s 2147.284us 1 1 100.00
chip_sw_example_manufacturer 132.780s 3171.672us 1 1 100.00
chip_sw_example_concurrency 137.400s 3226.978us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 194.330s 6402.021us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 431.610s 6014.927us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 731.890s 11323.036us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4173.840s 36200.755us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 45.830s 2049.094us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4173.840s 36200.755us 1 1 100.00
chip_csr_rw 431.610s 6014.927us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.590s 46.760us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 255.500s 4079.232us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 255.500s 4079.232us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 255.500s 4079.232us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 307.540s 3695.363us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 307.540s 3695.363us 1 1 100.00
chip_sw_uart_tx_rx_idx1 345.330s 3941.056us 1 1 100.00
chip_sw_uart_tx_rx_idx2 294.980s 3758.965us 1 1 100.00
chip_sw_uart_tx_rx_idx3 346.590s 4232.957us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1737.130s 13332.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1800.110s 12855.958us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 298.170s 4964.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 149.550s 4455.908us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 149.550s 4455.908us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 203.530s 3214.735us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 284.580s 5774.347us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 209.910s 3837.557us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 806.170s 12989.256us 1 1 100.00
chip_tap_straps_testunlock0 76.730s 2276.561us 1 1 100.00
chip_tap_straps_rma 247.380s 4622.254us 1 1 100.00
chip_tap_straps_prod 92.450s 2763.441us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 112.460s 2897.518us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 770.840s 8559.015us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 405.270s 6040.106us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 405.270s 6040.106us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 518.470s 6559.670us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 2558.740s 26061.834us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 354.430s 4410.244us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 572.480s 5553.021us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3298.810s 17998.220us 1 1 100.00
chip_sw_aes_enc_jitter_en 176.470s 2691.705us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 642.550s 5811.830us 1 1 100.00
chip_sw_hmac_enc_jitter_en 114.030s 2655.655us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 627.090s 6492.667us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 151.800s 2277.972us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 354.890s 5365.113us 1 1 100.00
chip_sw_clkmgr_jitter 117.230s 2601.829us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 223.360s 3587.682us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 428.850s 8031.655us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 265.480s 5108.887us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 103.190s 2246.915us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 265.480s 5108.887us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 99.840s 1874.297us 1 1 100.00
chip_sw_aes_smoketest 152.960s 3183.318us 1 1 100.00
chip_sw_aon_timer_smoketest 134.780s 3101.941us 1 1 100.00
chip_sw_clkmgr_smoketest 110.330s 1974.772us 1 1 100.00
chip_sw_csrng_smoketest 141.280s 2595.894us 1 1 100.00
chip_sw_entropy_src_smoketest 652.680s 6178.267us 1 1 100.00
chip_sw_gpio_smoketest 166.390s 3345.934us 1 1 100.00
chip_sw_hmac_smoketest 185.090s 2977.399us 1 1 100.00
chip_sw_kmac_smoketest 160.410s 2439.830us 1 1 100.00
chip_sw_otbn_smoketest 1142.090s 9502.526us 1 1 100.00
chip_sw_pwrmgr_smoketest 261.600s 5983.826us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 250.080s 5243.078us 1 1 100.00
chip_sw_rv_plic_smoketest 110.620s 2332.226us 1 1 100.00
chip_sw_rv_timer_smoketest 168.510s 2884.065us 1 1 100.00
chip_sw_rstmgr_smoketest 99.230s 2390.807us 1 1 100.00
chip_sw_sram_ctrl_smoketest 115.040s 2727.170us 1 1 100.00
chip_sw_uart_smoketest 179.560s 3319.869us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 110.880s 2657.071us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_functest 333.960s 4362.714us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7822.840s 61904.217us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2473.640s 14519.266us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 139.340s 5523.360us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 222.610s 3399.100us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 217.890s 3350.760us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7028.870s 54817.275us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7266.960s 56498.479us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 46.280s 2133.227us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 46.280s 2133.227us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4173.840s 36200.755us 1 1 100.00
chip_same_csr_outstanding 2592.240s 29263.840us 1 1 100.00
chip_csr_hw_reset 194.330s 6402.021us 1 1 100.00
chip_csr_rw 431.610s 6014.927us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4173.840s 36200.755us 1 1 100.00
chip_same_csr_outstanding 2592.240s 29263.840us 1 1 100.00
chip_csr_hw_reset 194.330s 6402.021us 1 1 100.00
chip_csr_rw 431.610s 6014.927us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 5.830s 36.757us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.010s 55.567us 1 1 100.00
xbar_smoke_large_delays 43.890s 7033.431us 1 1 100.00
xbar_smoke_slow_rsp 52.590s 5991.737us 1 1 100.00
xbar_random_zero_delays 15.750s 278.813us 1 1 100.00
xbar_random_large_delays 237.840s 41100.051us 1 1 100.00
xbar_random_slow_rsp 286.830s 33531.831us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 18.140s 269.839us 1 1 100.00
xbar_error_and_unmapped_addr 9.160s 119.797us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 20.550s 404.680us 1 1 100.00
xbar_error_and_unmapped_addr 9.160s 119.797us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 4.860s 72.711us 1 1 100.00
xbar_access_same_device_slow_rsp 25.450s 2720.760us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 16.760s 358.179us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 258.910s 11325.005us 1 1 100.00
xbar_stress_all_with_error 52.280s 1090.518us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 304.180s 5078.187us 1 1 100.00
xbar_stress_all_with_reset_error 145.320s 4266.583us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2473.640s 14519.266us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2435.440s 31310.987us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2507.330s 15587.170us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 1863.080s 10593.992us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2490.210s 15689.883us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2562.360s 15101.482us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2560.610s 15177.250us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2430.240s 15429.250us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 16.110s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 22.020s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 21.240s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21.110s 10.100us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 16.050s 10.240us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 16.960s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 17.630s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 20.350s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 22.870s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.400s 10.320us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 21.840s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.820s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.590s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 25.400s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.690s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 17.940s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.550s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.100s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.660s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 18.050s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.390s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 17.990s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.830s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.280s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.530s 10.300us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1872.050s 11226.709us 1 1 100.00
rom_e2e_asm_init_dev 2507.690s 15995.747us 1 1 100.00
rom_e2e_asm_init_prod 2484.960s 16247.568us 1 1 100.00
rom_e2e_asm_init_prod_end 2330.770s 15639.283us 1 1 100.00
rom_e2e_asm_init_rma 2303.300s 15148.528us 1 1 100.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 2381.560s 17160.946us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 4243.840s 28584.833us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2378.740s 16779.835us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2263.180s 16364.100us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3133.880s 34117.865us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3133.880s 34117.865us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 130.360s 2742.551us 1 1 100.00
chip_sw_aes_enc_jitter_en 176.470s 2691.705us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 125.420s 3322.707us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 111.610s 2436.735us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1391.700s 11523.941us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 162.790s 3134.907us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 291.340s 4937.488us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 402.560s 5732.581us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 546.310s 5346.582us 1 1 100.00
chip_plic_all_irqs_10 291.970s 3939.758us 1 1 100.00
chip_plic_all_irqs_20 316.180s 4300.267us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 182.750s 3492.269us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1097.100s 12202.085us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 194.910s 3603.381us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 119.580s 3301.748us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1427.200s 9790.197us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 827.750s 7052.028us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 741.920s 7905.367us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7208.630s 255699.507us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 272.600s 3845.137us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 261.600s 5983.826us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 272.600s 3845.137us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 485.360s 8166.358us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 485.360s 8166.358us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 230.220s 6131.966us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 355.760s 4679.319us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 612.490s 6322.276us 1 1 100.00
chip_sw_aes_idle 111.610s 2436.735us 1 1 100.00
chip_sw_hmac_enc_idle 158.030s 3338.614us 1 1 100.00
chip_sw_kmac_idle 153.920s 2441.454us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 228.090s 4982.461us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 185.030s 3549.606us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 266.520s 3773.830us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 261.600s 4210.048us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 869.280s 10818.892us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 347.280s 3595.094us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 365.410s 5102.674us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 321.230s 3477.321us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 353.360s 4090.270us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 343.860s 4593.653us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 337.550s 5039.972us 1 1 100.00
chip_sw_ast_clk_outputs 518.470s 6559.670us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 306.770s 7296.171us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 321.230s 3477.321us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 353.360s 4090.270us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 354.430s 4410.244us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 572.480s 5553.021us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3298.810s 17998.220us 1 1 100.00
chip_sw_aes_enc_jitter_en 176.470s 2691.705us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 642.550s 5811.830us 1 1 100.00
chip_sw_hmac_enc_jitter_en 114.030s 2655.655us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 627.090s 6492.667us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 151.800s 2277.972us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 354.890s 5365.113us 1 1 100.00
chip_sw_clkmgr_jitter 117.230s 2601.829us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 100.170s 2797.554us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 346.290s 5027.660us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 661.860s 7736.563us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3002.910s 24612.060us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 168.830s 3437.867us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 167.140s 3146.522us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 722.090s 8450.063us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 176.650s 3450.817us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 275.030s 5058.770us 1 1 100.00
chip_sw_flash_init_reduced_freq 1003.170s 23260.590us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2776.880s 25676.756us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 518.470s 6559.670us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 359.640s 4851.982us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 216.900s 3788.441us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 402.560s 5732.581us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1427.200s 9790.197us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 727.660s 6357.951us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 149.630s 2361.250us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 410.720s 7468.660us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 195.820s 3202.775us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3925.610s 23519.752us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 133.610s 2368.836us 1 1 100.00
chip_sw_edn_entropy_reqs 530.800s 5228.199us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 133.610s 2368.836us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 727.660s 6357.951us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 125.360s 2562.512us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1271.930s 19159.509us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 506.260s 4910.191us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 572.480s 5553.021us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 354.090s 4198.788us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 354.430s 4410.244us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3129.830s 43691.313us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1271.930s 19159.509us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 208.070s 3101.412us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1049.940s 8615.970us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 240.600s 4879.773us 1 1 100.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3129.830s 43691.313us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 240.600s 4879.773us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 240.600s 4879.773us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 240.600s 4879.773us 1 1 100.00
chip_sw_flash_lc_seed_hw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 240.600s 4879.773us 1 1 100.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 402.560s 5732.581us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 78.540s 4041.750us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 532.740s 4604.718us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 287.530s 5433.920us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 287.530s 5433.920us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 152.390s 3261.057us 1 1 100.00
chip_sw_hmac_enc_jitter_en 114.030s 2655.655us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 158.030s 3338.614us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1071.240s 8669.761us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 670.310s 5633.629us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 417.030s 4999.126us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 397.730s 5197.646us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 379.960s 5285.699us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 223.670s 3606.609us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1049.940s 8615.970us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 627.090s 6492.667us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1588.540s 11534.763us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1391.700s 11523.941us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2538.710s 14606.212us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 134.750s 2614.591us 1 1 100.00
chip_sw_kmac_mode_kmac 146.680s 2753.951us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 151.800s 2277.972us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1049.940s 8615.970us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 544.200s 10976.609us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 108.980s 2965.068us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 903.330s 7260.159us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 153.920s 2441.454us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 291.340s 4937.488us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 806.170s 12989.256us 1 1 100.00
chip_tap_straps_rma 247.380s 4622.254us 1 1 100.00
chip_tap_straps_prod 92.450s 2763.441us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 139.140s 2897.486us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 544.200s 10976.609us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 544.200s 10976.609us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 544.200s 10976.609us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1443.400s 10848.096us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 78.540s 4041.750us 1 1 100.00
chip_rv_dm_lc_disabled 107.820s 3522.368us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 240.600s 4879.773us 1 1 100.00
chip_sw_flash_rma_unlocked 3129.830s 43691.313us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 182.840s 3134.763us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 433.920s 4958.604us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 451.760s 4882.515us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 411.810s 5408.363us 0 1 0.00
chip_sw_lc_ctrl_transition 544.200s 10976.609us 1 1 100.00
chip_sw_keymgr_key_derivation 1049.940s 8615.970us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 314.630s 9010.925us 1 1 100.00
chip_sw_sram_ctrl_execution_main 513.630s 8242.034us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 306.770s 7296.171us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 347.280s 3595.094us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 365.410s 5102.674us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 321.230s 3477.321us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 353.360s 4090.270us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 343.860s 4593.653us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 337.550s 5039.972us 1 1 100.00
chip_tap_straps_dev 806.170s 12989.256us 1 1 100.00
chip_tap_straps_rma 247.380s 4622.254us 1 1 100.00
chip_tap_straps_prod 92.450s 2763.441us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 123.250s 2881.095us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 72.770s 2866.974us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 74.490s 2896.565us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 80.270s 3992.867us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 107.820s 3522.368us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1505.770s 28106.293us 1 1 100.00
chip_sw_lc_walkthrough 5 5 100.00
chip_sw_lc_walkthrough_dev 3456.050s 47380.761us 1 1 100.00
chip_sw_lc_walkthrough_prod 3615.980s 49109.046us 1 1 100.00
chip_sw_lc_walkthrough_prodend 594.670s 11051.290us 1 1 100.00
chip_sw_lc_walkthrough_rma 3862.940s 47893.264us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1505.770s 28106.293us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 69.800s 2489.601us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 83.730s 2991.601us 1 1 100.00
rom_volatile_raw_unlock 61.680s 2204.801us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3231.690s 17332.340us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3298.810s 17998.220us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 612.490s 6322.276us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 612.490s 6322.276us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 612.490s 6322.276us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 268.070s 3250.892us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 544.200s 10976.609us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1271.930s 19159.509us 1 1 100.00
chip_sw_otbn_mem_scramble 268.070s 3250.892us 1 1 100.00
chip_sw_keymgr_key_derivation 1049.940s 8615.970us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 256.890s 4548.712us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 127.960s 2682.569us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1271.930s 19159.509us 1 1 100.00
chip_sw_otbn_mem_scramble 268.070s 3250.892us 1 1 100.00
chip_sw_keymgr_key_derivation 1049.940s 8615.970us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 256.890s 4548.712us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 127.960s 2682.569us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 544.200s 10976.609us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 254.650s 4356.732us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 139.140s 2897.486us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 78.540s 4041.750us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 182.840s 3134.763us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 433.920s 4958.604us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 451.760s 4882.515us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 411.810s 5408.363us 0 1 0.00
chip_sw_lc_ctrl_transition 544.200s 10976.609us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 78.540s 4041.750us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 816.640s 8039.916us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 388.950s 9960.544us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1091.490s 25841.100us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 192.130s 6827.510us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 327.530s 7322.653us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 421.520s 7800.742us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1023.670s 22579.009us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 923.940s 13033.740us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 485.360s 8166.358us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 755.600s 11313.426us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 335.520s 4632.748us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 388.950s 9960.544us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 186.270s 3272.235us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 216.900s 5724.840us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 292.920s 7817.972us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 234.560s 4728.376us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 514.820s 12967.414us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 652.190s 8816.078us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 844.470s 8842.652us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1259.030s 27446.156us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 129.200s 3218.299us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 402.560s 5732.581us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 314.630s 9010.925us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 314.630s 9010.925us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 844.470s 8842.652us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 514.820s 12967.414us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 335.520s 4632.748us 1 1 100.00
chip_sw_pwrmgr_smoketest 261.600s 5983.826us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 201.910s 3588.223us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 275.190s 5045.314us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 185.130s 3343.084us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1097.100s 12202.085us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 160.290s 3689.207us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 402.560s 5732.581us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 827.750s 7052.028us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 449.510s 4901.952us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 454.600s 4438.334us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 176.240s 2683.835us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 127.960s 2682.569us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 275.190s 5045.314us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 275.190s 5045.314us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 677.280s 10225.333us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 796.830s 14105.323us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 201.910s 3588.223us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 161.000s 2436.492us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 291.070s 6733.730us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 247.380s 4622.254us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 107.820s 3522.368us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 546.310s 5346.582us 1 1 100.00
chip_plic_all_irqs_10 291.970s 3939.758us 1 1 100.00
chip_plic_all_irqs_20 316.180s 4300.267us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 102.510s 2166.981us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 181.660s 2909.109us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2473.640s 14519.266us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 454.140s 6730.585us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 212.930s 3168.808us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 234.460s 3787.427us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 160.890s 3552.892us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 256.890s 4548.712us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 354.890s 5365.113us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 457.160s 7926.356us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 304.910s 7432.939us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 513.630s 8242.034us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 402.560s 5732.581us 1 1 100.00
chip_sw_data_integrity_escalation 405.270s 6040.106us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 652.190s 8816.078us 1 1 100.00
chip_sw_sysrst_ctrl_reset 876.920s 23467.441us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 127.920s 2981.112us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 170.110s 3167.120us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 357.360s 4405.084us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 876.920s 23467.441us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 876.920s 23467.441us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 731.840s 11072.921us 0 1 0.00
chip_sw_sysrst_ctrl_flash_wp_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 731.840s 11072.921us 0 1 0.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 267.500s 6560.162us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3133.880s 34117.865us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 132.830s 2692.566us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 153.190s 2762.307us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 259.220s 4027.577us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 290.430s 3546.324us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1071.900s 7495.042us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4785.450s 31817.339us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1716.460s 12810.103us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 143.020s 2669.007us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 148.600s 2872.204us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 126.690s 2921.087us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9029.220s 71843.929us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1002.660s 6497.136us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 162.400s 3091.910us 0 1 0.00
rom_e2e_jtag_debug_dev 161.390s 4128.590us 0 1 0.00
rom_e2e_jtag_debug_rma 172.480s 3651.362us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 72.000s 2525.642us 0 1 0.00
rom_e2e_jtag_inject_dev 87.470s 2877.311us 0 1 0.00
rom_e2e_jtag_inject_rma 90.710s 2881.936us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.696s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 1 1 100.00
chip_sw_clkmgr_jitter_frequency 497.780s 5497.280us 1 1 100.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 284.530s 3222.555us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 522.730s 4301.979us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 770.670s 5702.953us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 187.950s 1966.039us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 576.960s 5079.953us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 50.690s 2304.121us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 132.500s 2661.157us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 244.540s 5443.803us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 214.820s 4216.501us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 844.470s 8842.652us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 162.400s 3091.910us 0 1 0.00
rom_e2e_jtag_debug_dev 161.390s 4128.590us 0 1 0.00
rom_e2e_jtag_debug_rma 172.480s 3651.362us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 401.970s 6543.534us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 402.560s 5732.581us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5174.040s 38226.431us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5174.040s 38226.431us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 131.980s 3622.883us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 307.540s 3695.363us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2773.930s 18887.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 164.060s 3529.768us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 395.920s 5019.348us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 1193.380s 21506.789us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 110.310s 2472.722us 1 1 100.00
chip_sw_otp_ctrl_descrambling 138.820s 2923.304us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 221.400s 4350.322us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 13.430s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 181.980s 2612.723us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31544) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 10433200027210507822543536664302420999961404007951796682330578836709586176128 214
UVM_ERROR @ 2133.227128 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31544) { a_addr: 'h10514 a_data: 'h9f4bb3b6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1bae1 d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2133.227128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 91999229707235451427547915865337514564243574182394228233867388233862939743033 233
UVM_ERROR @ 3522.368025 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10434 read out mismatch
UVM_INFO @ 3522.368025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31502) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 10062750731414548998052268407032027906280589652123806983260548377269590383427 221
UVM_ERROR @ 2049.093563 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31502) { a_addr: 'h10778 a_data: 'h7f1cde09 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h4 a_user: 'h1998b d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2049.093563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 72185777190433234029724201739393527979428598939230748736015778635240956547935 402
UVM_ERROR @ 3168.808040 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3168.808040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 83390648973273585805096988224743032621551908723136794641569174587082559218067 422
UVM_ERROR @ 5408.362722 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 5408.362722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 41525359550730854209633302590995066776708072162226798161014137582755487109792 393
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2661.157188 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2661.157188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 81860775188607496404071359719293447828112659064871476175034227747245425284712 394
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2361.250164 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2361.250164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 95566313595335028882518694739931932361014892826916057840287284296468796615650 422
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 5914890361408728997251444644517684261550236376554276197158596603366671966997 409
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 22988394749186397064524855089577644339387457151557397097330113816178535628526 447
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 112426189586643211814268102607036747413257688288645105266074872766835188180113 443
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 63133062661778426590759689893945015435409427564905892537506330683590357289769 449
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 62427098204159765744555497035527007657728302819161685033710288542820554287992 419
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 96659321292767095265300611208175956776587973351388157024858048478313819121907 417
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109948) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 104500241313313945942750490588898401772649970928722081709091395978524279628324 414
UVM_ERROR @ 5045.314151 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109948) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 5045.314151 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 79174703000221056381948426972446552558277927287199206929491790248172759320160 428
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 12967.413500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 12967.413500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 29945346717631730629831317210592130776164850087543160080288565695796744956332 399
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 5724.840000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5724.840000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
chip_sw_sysrst_ctrl_ec_rst_l 9838067372834080041050761425215656819306119846942471713927714322799361029255 402
UVM_ERROR @ 11072.921098 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
UVM_INFO @ 11072.921098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 25786128708478402603273233034376366959366514065966368297398127185203997269007 413
UVM_ERROR @ 34117.864980 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34117.864980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 78522364700071037932587863004670544207089877924244333154586880047219177919967 390
UVM_ERROR @ 3134.906631 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 3134.906631 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 62531906578850119938004454416755937804535566570005226485040696942817040476625 391
UVM_ERROR @ 3301.747840 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3301.747840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 15326257960033451135612601929659368429444310002612200816555423944351763130551 None
Job timed out after 240 minutes
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 68011445417244933666828305304119292963776665378574798274254111110120861101512 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.170s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 50610099847596127066672360442921792488101321973297220239066038164471898213592 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.173s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 112355575894756312337145741046205841126344102947823835915548311764033063295015 406
UVM_FATAL @ 2921.086606 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2921.086606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 85280341393591065760303386856469209799867827934817467868664323071934911625185 395
UVM_ERROR @ 3399.100000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3399.100000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 108135705430608315909686765663424361732375038340631365525919115038667458515964 402
UVM_ERROR @ 3350.760000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3350.760000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 51017623684580543455269239051293828598542258661958816800507782890645129390448 415
UVM_ERROR @ 26061.833894 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 26061.833894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 27434083430068113242046268000647847409584400622731088768740079721273778103387 518
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 98087851493884578243857681399748000106530622196817239589538508464768585993997 502
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 112102117637739492326869171698666741691525979187327591691797325434377268637789 494
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 100792553000192604475823867145728703385591194442608057342576325477942255176154 501
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 58788274730095575776333147871103093322246225218739883703938688638408026521060 499
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 105995488140654369896795791149000606662470092535879610192512823478355523272091 518
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 17692307174988644423431562976293711979834206597875843361586065029590384232770 503
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 50813004966187689187163612022201942200460968817458317044325551887292008076376 510
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 2158041096336825225407207639134338997145790945784570164156820216970259891120 506
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 82745359412463286297828742015169749752987552421032846997813267884022770875333 509
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 38854109584542300297677322776221358711619107769035532090669284686037003609323 537
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 36843246177429136541678276237921721225755330730875184213233969920789097930857 539
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 65259138610721551276348997470240288122647152871277215986604208017837425145294 555
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 85404530960408974292103771599250840011858051597946750893900741073215184421352 467
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 13311357446320880257749492665423282373494811913431941882528037022877610982428 468
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 89382377308437829291537132058098736732382006109014690885760214550442978697557 471
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 59647693435094739686648511927949178877165506038824103235924129448625424023008 522
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 58376285633940202548834734005371271031040354995535482682895367654831960509512 472
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 48787979154440636307708984524657398901534907303611049039018470793185600572245 535
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 30350587382582891887533640813359103360867281641584206488925472358848333027984 466
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 26223564903384942626816734990534773867952124629182289303960870675989441365168 481
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 69900097667498536556827468419437381487367839891446295027892272585361927922109 477
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 26798896114489472730890527377344873954250619572164629437957342271796191670088 474
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 111490479464746182894700291666218544610088820781059599055289247908420701189254 545
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 38847207210267906469929912962306928060381950946096788456569470881881411365504 517
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_test_unlocked0 29350741741504385066669379168114806843363165320751733660986205452258295191100 428
UVM_ERROR @ 3091.910037 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
UVM_INFO @ 3091.910037 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 23412163563334358492685539624877997765162234047687553500119134880487943202192 429
UVM_ERROR @ 17160.946327 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 17160.946327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 73486999050856001379036563117043663791076837688999516160403981331753449820508 421
UVM_ERROR @ 16779.835495 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16779.835495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---