Simulation Results: clkmgr

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.71 %
  • code
  • 98.25 %
  • assert
  • 95.48 %
  • func
  • 84.39 %
  • line
  • 99.00 %
  • branch
  • 98.65 %
  • cond
  • 94.39 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.95%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.940s 31.341us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.950s 52.450us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.770s 17.274us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.810s 355.919us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.200s 148.242us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.160s 37.455us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.770s 17.274us 1 1 100.00
clkmgr_csr_aliasing 1.200s 148.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.810s 78.638us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.820s 31.704us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.750s 17.242us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 15.334us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.940s 31.341us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 9.090s 1883.064us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 8.210s 1818.234us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 9.090s 1883.064us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 11.930s 3376.415us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.860s 20.813us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.450s 70.670us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.450s 70.670us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.950s 52.450us 1 1 100.00
clkmgr_csr_rw 0.770s 17.274us 1 1 100.00
clkmgr_csr_aliasing 1.200s 148.242us 1 1 100.00
clkmgr_same_csr_outstanding 0.970s 39.474us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.950s 52.450us 1 1 100.00
clkmgr_csr_rw 0.770s 17.274us 1 1 100.00
clkmgr_csr_aliasing 1.200s 148.242us 1 1 100.00
clkmgr_same_csr_outstanding 0.970s 39.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_tl_intg_err 2.340s 155.777us 1 1 100.00
clkmgr_sec_cm 0.960s 26.283us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.900s 158.691us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.900s 158.691us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.900s 158.691us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.900s 158.691us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.480s 199.329us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.340s 155.777us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 9.090s 1883.064us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 8.210s 1818.234us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.900s 158.691us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.980s 24.138us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.100s 45.565us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.090s 66.651us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 0 1 0.00
clkmgr_clk_handshake_intersig_mubi 0.670s 2.767us 0 1 0.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.700s 27.107us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.770s 17.274us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.960s 26.283us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 17.274us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 17.274us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.960s 26.283us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.910s 494.007us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 29.980s 6458.166us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 16280836544426581513071203158941671855846228149407934957571262167270624702558 71
UVM_ERROR @ 2766895 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (8 [0x8] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 2766895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 99717520583501862565343028119693818081313756889796494327007706499363232449603 93
UVM_ERROR @ 26283435 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 26283435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---