Simulation Results: edn

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.56 %
  • code
  • 80.31 %
  • assert
  • 95.01 %
  • func
  • 81.35 %
  • line
  • 97.17 %
  • branch
  • 90.10 %
  • cond
  • 85.72 %
  • toggle
  • 79.64 %
  • FSM
  • 48.92 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.920s 24.464us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 51.346us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 67.882us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.330s 217.697us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.290s 46.737us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.930s 20.664us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 67.882us 1 1 100.00
edn_csr_aliasing 1.290s 46.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.300s 43.623us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.300s 43.623us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.300s 43.623us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.090s 20.952us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.150s 42.477us 1 1 100.00
errs 1 1 100.00
edn_err 1.050s 32.156us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 19.187us 1 1 100.00
edn_disable_auto_req_mode 0.960s 90.985us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.540s 443.703us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 24.507us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 17.821us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.070s 447.875us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.070s 447.875us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 51.346us 1 1 100.00
edn_csr_rw 0.770s 67.882us 1 1 100.00
edn_csr_aliasing 1.290s 46.737us 1 1 100.00
edn_same_csr_outstanding 0.920s 21.868us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 51.346us 1 1 100.00
edn_csr_rw 0.770s 67.882us 1 1 100.00
edn_csr_aliasing 1.290s 46.737us 1 1 100.00
edn_same_csr_outstanding 0.920s 21.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.360s 93.133us 1 1 100.00
edn_sec_cm 7.350s 645.072us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 19.775us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.150s 42.477us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.350s 645.072us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.350s 645.072us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.350s 645.072us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.350s 645.072us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.150s 42.477us 1 1 100.00
edn_sec_cm 7.350s 645.072us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.150s 42.477us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.360s 93.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 77.390s 16680.404us 1 1 100.00

Error Messages

   Test seed line log context