Simulation Results: edn

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.20 %
  • code
  • 83.15 %
  • assert
  • 97.14 %
  • func
  • 81.30 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 89.46 %
  • toggle
  • 94.09 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 39.369us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.930s 23.835us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.010s 16.831us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.210s 1448.130us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 15.757us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.870s 44.844us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.010s 16.831us 1 1 100.00
edn_csr_aliasing 1.030s 15.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.050s 66.957us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.050s 66.957us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.050s 66.957us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.760s 24.517us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 321.252us 1 1 100.00
errs 1 1 100.00
edn_err 1.080s 23.414us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 10.780us 1 1 100.00
edn_disable_auto_req_mode 0.960s 51.409us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.530s 667.232us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 47.134us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.770s 36.533us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.860s 181.453us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.860s 181.453us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.930s 23.835us 1 1 100.00
edn_csr_rw 1.010s 16.831us 1 1 100.00
edn_csr_aliasing 1.030s 15.757us 1 1 100.00
edn_same_csr_outstanding 1.120s 216.072us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.930s 23.835us 1 1 100.00
edn_csr_rw 1.010s 16.831us 1 1 100.00
edn_csr_aliasing 1.030s 15.757us 1 1 100.00
edn_same_csr_outstanding 1.120s 216.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.820s 300.065us 1 1 100.00
edn_sec_cm 12.610s 1400.832us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.770s 30.804us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 321.252us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 12.610s 1400.832us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 12.610s 1400.832us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 12.610s 1400.832us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 12.610s 1400.832us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 321.252us 1 1 100.00
edn_sec_cm 12.610s 1400.832us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 321.252us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.820s 300.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.140s 2191.260us 1 1 100.00

Error Messages

   Test seed line log context