Simulation Results: flash_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 94.04 %
  • assert
  • 96.62 %
  • func
  • 95.64 %
  • line
  • 95.96 %
  • branch
  • 97.10 %
  • cond
  • 94.11 %
  • toggle
  • 97.98 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
98.46%
V2S
97.73%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 64.670s 195.614us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.890s 19.024us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 18.250s 170.290us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.750s 22.313us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 49.790s 3405.436us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 19.430s 962.981us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.980s 144.615us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.750s 22.313us 1 1 100.00
flash_ctrl_csr_aliasing 19.430s 962.981us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.000s 17.700us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 7.600s 19.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.670s 68.598us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 52.840s 121.632us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1356.920s 150514.537us 1 1 100.00
flash_ctrl_hw_rma_reset 689.580s 480328.998us 1 1 100.00
flash_ctrl_lcmgr_intg 5.560s 25.738us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 994.480s 645132.452us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 304.250s 4170.496us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 10.420s 41.079us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1624.790s 93168.607us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 34.550s 333.536us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.010s 27.324us 1 1 100.00
flash_ctrl_rw_evict_all_en 18.740s 58.802us 1 1 100.00
flash_ctrl_re_evict 21.080s 108.657us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 159.070s 5546.641us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 159.070s 5546.641us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 285.430s 63559.725us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 17.700s 4781.519us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 322.560s 1629.260us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 370.860s 18575.827us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 358.940s 1524.593us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 651.150s 1717.243us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 11.250s 79.684us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 114.050s 3480.427us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.480s 60.647us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 9.980s 30.909us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 411.060s 853.197us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 87.500s 1701.330us 1 1 100.00
flash_ctrl_otp_reset 51.480s 118.267us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1356.920s 150514.537us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 78.010s 1542.603us 1 1 100.00
flash_ctrl_intr_wr 64.070s 8995.843us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 207.780s 35513.400us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 203.940s 115513.867us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 38.230s 3176.438us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 48.230s 13620.459us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.990s 427.764us 1 1 100.00
flash_ctrl_ro_derr 104.300s 11883.010us 1 1 100.00
flash_ctrl_rw_derr 135.820s 2523.611us 1 1 100.00
flash_ctrl_derr_detect 99.310s 10184.775us 1 1 100.00
flash_ctrl_integrity 347.710s 4463.614us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.070s 120.112us 1 1 100.00
flash_ctrl_ro_serr 88.370s 709.322us 1 1 100.00
flash_ctrl_rw_serr 120.690s 8971.846us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 57.350s 928.938us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 47.870s 3359.555us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 102.740s 2435.086us 1 1 100.00
flash_ctrl_write_word_sweep 9.920s 525.947us 1 1 100.00
flash_ctrl_read_word_sweep 8.050s 27.135us 1 1 100.00
flash_ctrl_ro 70.330s 2407.564us 1 1 100.00
flash_ctrl_rw 9.870s 20.999us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.560s 1570.973us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 635.280s 234119.316us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 35.370s 10062.871us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.050s 189.589us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.340s 32.064us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.440s 61.891us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.440s 61.891us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.250s 170.290us 1 1 100.00
flash_ctrl_csr_rw 8.750s 22.313us 1 1 100.00
flash_ctrl_csr_aliasing 19.430s 962.981us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.350s 470.612us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.250s 170.290us 1 1 100.00
flash_ctrl_csr_rw 8.750s 22.313us 1 1 100.00
flash_ctrl_csr_aliasing 19.430s 962.981us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.350s 470.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.730s 136.083us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 26.730s 136.083us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.730s 136.083us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 26.730s 136.083us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 20.810s 158.802us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 360.270s 875.986us 1 1 100.00
flash_ctrl_sec_cm 1520.940s 2548.396us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 360.270s 875.986us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 360.270s 875.986us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 19.420s 63.022us 1 1 100.00
flash_ctrl_wr_intg 7.040s 151.864us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 64.670s 195.614us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 51.480s 118.267us 1 1 100.00
flash_ctrl_disable 9.480s 60.647us 1 1 100.00
flash_ctrl_sec_info_access 48.650s 3244.472us 1 1 100.00
flash_ctrl_connect 9.980s 30.909us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.670s 32.557us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.750s 22.313us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.730s 136.083us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.750s 22.313us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.730s 136.083us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.750s 22.313us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.730s 136.083us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.480s 60.647us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 19.420s 63.022us 1 1 100.00
flash_ctrl_access_after_disable 5.620s 71.666us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.170s 165.989us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.480s 60.647us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 17.700s 4781.519us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 9.870s 20.999us 0 1 0.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 120.690s 8971.846us 1 1 100.00
flash_ctrl_rw_derr 135.820s 2523.611us 1 1 100.00
flash_ctrl_integrity 347.710s 4463.614us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1356.920s 150514.537us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1520.940s 2548.396us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1520.940s 2548.396us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1520.940s 2548.396us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1520.940s 2548.396us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.890s 883.456us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.800s 80.413us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.930s 75.527us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1520.940s 2548.396us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1520.940s 2548.396us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1520.940s 2548.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.010s 76.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 280.960s 2821.574us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly
flash_ctrl_rw 76975979114603619082774045787744161091567569684269303140389135982522420197732 105
UVM_ERROR @ 20999.0 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 20999.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---