Simulation Results: hmac

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.01 %
  • code
  • 98.57 %
  • assert
  • 96.42 %
  • func
  • 45.03 %
  • line
  • 99.74 %
  • branch
  • 99.50 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.820s 941.997us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.850s 23.802us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.830s 34.438us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.920s 122.654us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.240s 110.773us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.730s 25.561us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.830s 34.438us 1 1 100.00
hmac_csr_aliasing 2.240s 110.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 31.410s 8635.442us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 23.250s 610.939us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.300s 343.377us 1 1 100.00
hmac_test_sha384_vectors 332.560s 8905.027us 1 1 100.00
hmac_test_sha512_vectors 20.780s 1189.963us 1 1 100.00
hmac_test_hmac256_vectors 7.010s 230.677us 1 1 100.00
hmac_test_hmac384_vectors 9.010s 256.994us 1 1 100.00
hmac_test_hmac512_vectors 12.240s 1539.390us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.290s 2934.175us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 1020.240s 30074.200us 1 1 100.00
error 1 1 100.00
hmac_error 36.120s 3846.861us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 41.800s 3242.549us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.820s 941.997us 1 1 100.00
hmac_long_msg 31.410s 8635.442us 1 1 100.00
hmac_back_pressure 23.250s 610.939us 1 1 100.00
hmac_datapath_stress 1020.240s 30074.200us 1 1 100.00
hmac_burst_wr 8.290s 2934.175us 1 1 100.00
hmac_stress_all 86.360s 29162.622us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.820s 941.997us 1 1 100.00
hmac_long_msg 31.410s 8635.442us 1 1 100.00
hmac_back_pressure 23.250s 610.939us 1 1 100.00
hmac_datapath_stress 1020.240s 30074.200us 1 1 100.00
hmac_wipe_secret 41.800s 3242.549us 1 1 100.00
hmac_test_sha256_vectors 8.300s 343.377us 1 1 100.00
hmac_test_sha384_vectors 332.560s 8905.027us 1 1 100.00
hmac_test_sha512_vectors 20.780s 1189.963us 1 1 100.00
hmac_test_hmac256_vectors 7.010s 230.677us 1 1 100.00
hmac_test_hmac384_vectors 9.010s 256.994us 1 1 100.00
hmac_test_hmac512_vectors 12.240s 1539.390us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.820s 941.997us 1 1 100.00
hmac_long_msg 31.410s 8635.442us 1 1 100.00
hmac_back_pressure 23.250s 610.939us 1 1 100.00
hmac_datapath_stress 1020.240s 30074.200us 1 1 100.00
hmac_burst_wr 8.290s 2934.175us 1 1 100.00
hmac_error 36.120s 3846.861us 1 1 100.00
hmac_wipe_secret 41.800s 3242.549us 1 1 100.00
hmac_test_sha256_vectors 8.300s 343.377us 1 1 100.00
hmac_test_sha384_vectors 332.560s 8905.027us 1 1 100.00
hmac_test_sha512_vectors 20.780s 1189.963us 1 1 100.00
hmac_test_hmac256_vectors 7.010s 230.677us 1 1 100.00
hmac_test_hmac384_vectors 9.010s 256.994us 1 1 100.00
hmac_test_hmac512_vectors 12.240s 1539.390us 1 1 100.00
hmac_stress_all 86.360s 29162.622us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 86.360s 29162.622us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.880s 27.041us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.780s 30.331us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.570s 354.432us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.570s 354.432us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.850s 23.802us 1 1 100.00
hmac_csr_rw 0.830s 34.438us 1 1 100.00
hmac_csr_aliasing 2.240s 110.773us 1 1 100.00
hmac_same_csr_outstanding 1.650s 151.381us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.850s 23.802us 1 1 100.00
hmac_csr_rw 0.830s 34.438us 1 1 100.00
hmac_csr_aliasing 2.240s 110.773us 1 1 100.00
hmac_same_csr_outstanding 1.650s 151.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.360s 90.687us 1 1 100.00
hmac_tl_intg_err 2.570s 165.869us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.570s 165.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.820s 941.997us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.720s 64.624us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 74.730s 24030.523us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.080s 1077.944us 1 1 100.00

Error Messages

   Test seed line log context