| V1 |
|
100.00% |
| V2 |
|
91.84% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_smoke | 1 | 1 | 100.00 | |||
| i2c_host_smoke | 28.970s | 2188.279us | 1 | 1 | 100.00 | |
| target_smoke | 1 | 1 | 100.00 | |||
| i2c_target_smoke | 7.210s | 808.933us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| i2c_csr_hw_reset | 0.630s | 51.344us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| i2c_csr_rw | 0.710s | 18.854us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| i2c_csr_bit_bash | 3.560s | 475.102us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| i2c_csr_aliasing | 1.170s | 682.333us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| i2c_csr_mem_rw_with_rand_reset | 0.850s | 30.247us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| i2c_csr_rw | 0.710s | 18.854us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.170s | 682.333us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_error_intr | 0 | 1 | 0.00 | |||
| i2c_host_error_intr | 1.370s | 336.316us | 0 | 1 | 0.00 | |
| host_stress_all | 0 | 1 | 0.00 | |||
| i2c_host_stress_all | 76.910s | 18538.632us | 0 | 1 | 0.00 | |
| host_maxperf | 1 | 1 | 100.00 | |||
| i2c_host_perf | 82.330s | 49816.215us | 1 | 1 | 100.00 | |
| host_override | 1 | 1 | 100.00 | |||
| i2c_host_override | 0.620s | 24.518us | 1 | 1 | 100.00 | |
| host_fifo_watermark | 1 | 1 | 100.00 | |||
| i2c_host_fifo_watermark | 37.720s | 12651.836us | 1 | 1 | 100.00 | |
| host_fifo_overflow | 1 | 1 | 100.00 | |||
| i2c_host_fifo_overflow | 38.270s | 2087.704us | 1 | 1 | 100.00 | |
| host_fifo_reset | 3 | 3 | 100.00 | |||
| i2c_host_fifo_reset_fmt | 0.730s | 252.221us | 1 | 1 | 100.00 | |
| i2c_host_fifo_fmt_empty | 9.060s | 549.842us | 1 | 1 | 100.00 | |
| i2c_host_fifo_reset_rx | 2.740s | 272.582us | 1 | 1 | 100.00 | |
| host_fifo_full | 1 | 1 | 100.00 | |||
| i2c_host_fifo_full | 45.840s | 2777.206us | 1 | 1 | 100.00 | |
| host_timeout | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 18.200s | 614.388us | 1 | 1 | 100.00 | |
| i2c_host_mode_toggle | 0 | 1 | 0.00 | |||
| i2c_host_mode_toggle | 3.910s | 160.022us | 0 | 1 | 0.00 | |
| target_glitch | 0 | 1 | 0.00 | |||
| i2c_target_glitch | 2.030s | 526.777us | 0 | 1 | 0.00 | |
| target_stress_all | 1 | 1 | 100.00 | |||
| i2c_target_stress_all | 339.820s | 35011.254us | 1 | 1 | 100.00 | |
| target_maxperf | 1 | 1 | 100.00 | |||
| i2c_target_perf | 3.890s | 756.631us | 1 | 1 | 100.00 | |
| target_fifo_empty | 2 | 2 | 100.00 | |||
| i2c_target_stress_rd | 8.370s | 4749.464us | 1 | 1 | 100.00 | |
| i2c_target_intr_smoke | 5.540s | 1665.653us | 1 | 1 | 100.00 | |
| target_fifo_reset | 2 | 2 | 100.00 | |||
| i2c_target_fifo_reset_acq | 0.930s | 388.765us | 1 | 1 | 100.00 | |
| i2c_target_fifo_reset_tx | 1.100s | 198.375us | 1 | 1 | 100.00 | |
| target_fifo_full | 3 | 3 | 100.00 | |||
| i2c_target_stress_wr | 34.740s | 54681.326us | 1 | 1 | 100.00 | |
| i2c_target_stress_rd | 8.370s | 4749.464us | 1 | 1 | 100.00 | |
| i2c_target_intr_stress_wr | 7.730s | 3421.278us | 1 | 1 | 100.00 | |
| target_timeout | 1 | 1 | 100.00 | |||
| i2c_target_timeout | 4.290s | 1228.824us | 1 | 1 | 100.00 | |
| target_clock_stretch | 1 | 1 | 100.00 | |||
| i2c_target_stretch | 7.660s | 4091.580us | 1 | 1 | 100.00 | |
| bad_address | 1 | 1 | 100.00 | |||
| i2c_target_bad_addr | 3.180s | 897.539us | 1 | 1 | 100.00 | |
| target_mode_glitch | 1 | 1 | 100.00 | |||
| i2c_target_hrst | 1.250s | 134.230us | 1 | 1 | 100.00 | |
| target_fifo_watermark | 2 | 2 | 100.00 | |||
| i2c_target_fifo_watermarks_acq | 1.350s | 882.316us | 1 | 1 | 100.00 | |
| i2c_target_fifo_watermarks_tx | 1.130s | 140.292us | 1 | 1 | 100.00 | |
| host_mode_config_perf | 2 | 2 | 100.00 | |||
| i2c_host_perf | 82.330s | 49816.215us | 1 | 1 | 100.00 | |
| i2c_host_perf_precise | 14.660s | 1920.826us | 1 | 1 | 100.00 | |
| host_mode_clock_stretching | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 18.200s | 614.388us | 1 | 1 | 100.00 | |
| target_mode_tx_stretch_ctrl | 1 | 1 | 100.00 | |||
| i2c_target_tx_stretch_ctrl | 3.050s | 279.840us | 1 | 1 | 100.00 | |
| target_mode_nack_generation | 3 | 3 | 100.00 | |||
| i2c_target_nack_acqfull | 2.160s | 2253.963us | 1 | 1 | 100.00 | |
| i2c_target_nack_acqfull_addr | 1.700s | 1916.108us | 1 | 1 | 100.00 | |
| i2c_target_nack_txstretch | 1.200s | 260.131us | 1 | 1 | 100.00 | |
| host_mode_halt_on_nak | 1 | 1 | 100.00 | |||
| i2c_host_may_nack | 3.760s | 460.231us | 1 | 1 | 100.00 | |
| target_mode_smbus_maxlen | 1 | 1 | 100.00 | |||
| i2c_target_smbus_maxlen | 1.710s | 483.752us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| i2c_alert_test | 0.680s | 25.119us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| i2c_intr_test | 0.620s | 78.105us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| i2c_tl_errors | 1.030s | 99.958us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| i2c_tl_errors | 1.030s | 99.958us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| i2c_csr_hw_reset | 0.630s | 51.344us | 1 | 1 | 100.00 | |
| i2c_csr_rw | 0.710s | 18.854us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.170s | 682.333us | 1 | 1 | 100.00 | |
| i2c_same_csr_outstanding | 0.990s | 843.552us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| i2c_csr_hw_reset | 0.630s | 51.344us | 1 | 1 | 100.00 | |
| i2c_csr_rw | 0.710s | 18.854us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.170s | 682.333us | 1 | 1 | 100.00 | |
| i2c_same_csr_outstanding | 0.990s | 843.552us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| i2c_sec_cm | 0.860s | 148.443us | 1 | 1 | 100.00 | |
| i2c_tl_intg_err | 1.300s | 269.966us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| i2c_tl_intg_err | 1.300s | 269.966us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_host_stress_all_with_rand_reset | 2.450s | 163.059us | 0 | 1 | 0.00 | |
| target_error_intr | 0 | 1 | 0.00 | |||
| i2c_target_unexp_stop | 1.070s | 223.640us | 0 | 1 | 0.00 | |
| target_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_target_stress_all_with_rand_reset | 7.300s | 1261.150us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between | ||||
| i2c_host_error_intr | 96472273763458529672971208615517872582113710325556616669410294482830063428252 | 91 |
UVM_ERROR @ 336315600 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 336315600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_host_stress_all | 75574165189382878977123378146571051905402518923279758299138681496984220908370 | 128 |
UVM_ERROR @ 18538632015 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 18538632015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_target_stress_all_with_rand_reset | 50882677602631478667169097782025885235225195690341519422897882753891750796811 | 91 |
UVM_ERROR @ 1261150202 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 1261150202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between | ||||
| i2c_target_glitch | 10465847813276355765882952568197179369498673399066977286768745573670486475674 | 81 |
UVM_ERROR @ 526777375 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 526777375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' | ||||
| i2c_target_unexp_stop | 100368488024180947929154783903726653371059110572720318599983512224950369905869 | 76 |
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 223639585 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 223639585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| i2c_host_stress_all_with_rand_reset | 99638568118286421874751277224874227301246663874239253331690625983905339910556 | 91 |
UVM_ERROR @ 163058884 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 163058884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: | ||||
| i2c_host_mode_toggle | 17525597004305967765070863161224603103725755669443292388627265859077206838920 | 82 |
UVM_ERROR @ 160022235 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @68212
|
|