Simulation Results: keymgr

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.16 %
  • code
  • 93.09 %
  • assert
  • 97.49 %
  • func
  • 55.89 %
  • line
  • 98.70 %
  • branch
  • 97.76 %
  • cond
  • 94.67 %
  • toggle
  • 88.28 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.930s 117.121us 1 1 100.00
random 1 1 100.00
keymgr_random 3.050s 95.536us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.880s 22.583us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.310s 163.942us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.280s 267.506us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.470s 732.910us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.420s 34.407us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.310s 163.942us 1 1 100.00
keymgr_csr_aliasing 5.470s 732.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.780s 54.512us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 20.320s 1318.199us 1 1 100.00
keymgr_sideload_kmac 1.810s 55.972us 1 1 100.00
keymgr_sideload_aes 1.970s 214.247us 1 1 100.00
keymgr_sideload_otbn 1.680s 136.202us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.420s 32.100us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 4.220s 133.247us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.440s 415.393us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.550s 499.134us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.980s 174.914us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.150s 98.180us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 8.290s 487.338us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.910s 13.290us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.730s 13.866us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.890s 1123.768us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.890s 1123.768us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.880s 22.583us 1 1 100.00
keymgr_csr_rw 1.310s 163.942us 1 1 100.00
keymgr_csr_aliasing 5.470s 732.910us 1 1 100.00
keymgr_same_csr_outstanding 1.570s 569.264us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.880s 22.583us 1 1 100.00
keymgr_csr_rw 1.310s 163.942us 1 1 100.00
keymgr_csr_aliasing 5.470s 732.910us 1 1 100.00
keymgr_same_csr_outstanding 1.570s 569.264us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 4.730s 1428.754us 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.580s 555.494us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.580s 555.494us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.580s 555.494us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.580s 555.494us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 6.990s 796.893us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 4.730s 1428.754us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.580s 555.494us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.780s 54.512us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 1.310s 163.942us 1 1 100.00
keymgr_random 3.050s 95.536us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 1.310s 163.942us 1 1 100.00
keymgr_random 3.050s 95.536us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 1.310s 163.942us 1 1 100.00
keymgr_random 3.050s 95.536us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 4.220s 133.247us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.980s 174.914us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.980s 174.914us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.050s 95.536us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.440s 42.392us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.670s 1193.814us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 4.220s 133.247us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.670s 1193.814us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.670s 1193.814us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.670s 1193.814us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.740s 5434.949us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.670s 1193.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 4.300s 233.884us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 104490237635723777198682351184819023562524687124102730841509318194902047117322 381
UVM_ERROR @ 233883571 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 233883571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---