Simulation Results: lc_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.57 %
  • code
  • 84.20 %
  • assert
  • 94.13 %
  • func
  • 90.39 %
  • line
  • 97.08 %
  • branch
  • 93.82 %
  • cond
  • 79.59 %
  • toggle
  • 79.21 %
  • FSM
  • 71.28 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.790s 179.115us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.060s 196.140us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.010s 20.198us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.370s 43.117us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 117.640us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.100s 23.420us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.010s 20.198us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 117.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.330s 188.782us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.360s 1259.329us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.900s 54.236us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.360s 500.266us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.680s 411.070us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_prog_failure 2.360s 500.266us 1 1 100.00
lc_ctrl_errors 5.680s 411.070us 1 1 100.00
lc_ctrl_security_escalation 4.450s 3067.726us 1 1 100.00
lc_ctrl_jtag_state_failure 8.980s 1588.660us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.640s 778.776us 1 1 100.00
lc_ctrl_jtag_errors 21.930s 2167.737us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 8.290s 851.045us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.500s 515.831us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.640s 778.776us 1 1 100.00
lc_ctrl_jtag_errors 21.930s 2167.737us 1 1 100.00
lc_ctrl_jtag_access 6.050s 206.363us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.080s 902.700us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.610s 154.979us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.280s 252.169us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.780s 4438.440us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.530s 2226.069us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.560s 163.683us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.110s 481.114us 1 1 100.00
lc_ctrl_jtag_alert_test 1.340s 157.540us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 9.480s 941.789us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.180s 15.620us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 44.270s 4563.037us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 89.100us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.590s 85.113us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.590s 85.113us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.060s 196.140us 1 1 100.00
lc_ctrl_csr_rw 1.010s 20.198us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 117.640us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.180s 34.652us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.060s 196.140us 1 1 100.00
lc_ctrl_csr_rw 1.010s 20.198us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 117.640us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.180s 34.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
lc_ctrl_tl_intg_err 2.170s 326.821us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.170s 326.821us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.360s 1259.329us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.530s 11.127us 0 1 0.00
lc_ctrl_sec_cm 5.340s 141.024us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.450s 3067.726us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.330s 188.782us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.500s 515.831us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.680s 295.891us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.680s 295.891us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.030s 1765.508us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.230s 528.205us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.230s 528.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.300s 90.156us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 90188031866826634883028512268992880686088255471350908429743131913654877165072 123
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 11126672 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 11126672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 53861859329831423194023592980019935911942778256229224304544349857708843065419 865
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1588660032 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1588660032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 76216658893542429021819159830555263287616028009705347777768155906823170894607 12738
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 4563036818 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4563036818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32047478033401334215550598249664945529852575688910734744601880199723841776820 424
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 90156336 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 90156336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---