Simulation Results: lc_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.72 %
  • code
  • 84.41 %
  • assert
  • 93.85 %
  • func
  • 87.90 %
  • line
  • 96.93 %
  • branch
  • 93.47 %
  • cond
  • 79.01 %
  • toggle
  • 81.07 %
  • FSM
  • 71.58 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.920s 69.941us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.900s 241.903us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 23.475us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.380s 42.505us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 181.334us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.370s 124.082us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 23.475us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 181.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.880s 102.489us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.370s 1041.632us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.870s 42.356us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.570s 95.299us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.690s 887.192us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_prog_failure 1.570s 95.299us 1 1 100.00
lc_ctrl_errors 5.690s 887.192us 1 1 100.00
lc_ctrl_security_escalation 4.620s 1550.312us 1 1 100.00
lc_ctrl_jtag_state_failure 1.460s 99.119us 0 1 0.00
lc_ctrl_jtag_prog_failure 5.110s 876.464us 1 1 100.00
lc_ctrl_jtag_errors 31.740s 3272.935us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 2.120s 66.318us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.800s 1094.355us 0 1 0.00
lc_ctrl_jtag_prog_failure 5.110s 876.464us 1 1 100.00
lc_ctrl_jtag_errors 31.740s 3272.935us 1 1 100.00
lc_ctrl_jtag_access 1.380s 66.919us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.720s 3149.397us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.090s 139.123us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.780s 158.401us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.320s 804.144us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.720s 639.231us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.190s 81.528us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.320s 195.787us 1 1 100.00
lc_ctrl_jtag_alert_test 1.880s 69.088us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.700s 885.456us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.830s 33.869us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 1.670s 27.299us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.110s 45.163us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.470s 99.624us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.470s 99.624us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.900s 241.903us 1 1 100.00
lc_ctrl_csr_rw 0.820s 23.475us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 181.334us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.900s 78.460us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.900s 241.903us 1 1 100.00
lc_ctrl_csr_rw 0.820s 23.475us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 181.334us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.900s 78.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 70.063us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 70.063us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.370s 1041.632us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.100s 170.516us 0 1 0.00
lc_ctrl_sec_cm 8.650s 681.999us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.620s 1550.312us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 1.880s 102.489us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.800s 1094.355us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.780s 260.494us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.780s 260.494us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 11.600s 2650.192us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.420s 803.730us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.420s 803.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.740s 116.158us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 42531856017085911276499802878932629398783685574829419745549492047966635763839 633
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 170515695 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 170515695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 52959295508924387770356137641610752252361983486542777952578097724803904412537 242
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 99118933 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 99118933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 108049193242943586453289080311098348993698619618356916888321924102432603677026 657
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1094355197 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1094355197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 105279947652220823818582024859422017227745928713164939751142934449363414659909 460
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 27298828 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 27298828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 31243177244136393314637683436892490232609868484019174565421086471889230768744 147
UVM_ERROR @ 116158252 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 116158252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---